Gate Plug Isolation for Transistor Gate Short Defects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Transistor gate short defects occur due to material deposition in gate plug regions during patterning processes, exacerbated by alignment and critical dimension tolerances challenges in fabricating gate and contact electrodes.
Innovation Solution
The method involves forming gate electrode lines, depositing a first electrically insulative material, performing a gate cut to isolate gate electrodes, and using a second electrically insulative material with a different composition for the gate plug, which reduces the likelihood of contact electrode material deposition in the gate plug region, thereby minimizing short defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If patterning processes are used to fabricate gate electrodes and contact electrodes, then electrical energy routing is achieved, but material of contact electrodes may be deposited in gate plug region causing transistor gate short defects
Solution Approach 1:
A gate plug structure is introduced as an intermediary element between the contact electrode and the gate electrode. The gate plug is formed with a material composition different from the contact electrode material, serving as a barrier to prevent contact electrode material from being deposited in the gate plug region during patterning processes, thereby eliminating the direct harmful interaction between contact electrode material and gate electrode
2Manufacturing precision
If alignment and critical dimension tolerances are reduced for gate and contact electrodes, then fabrication precision is improved, but defects between material of gate electrodes and contact electrodes are exacerbated
Solution Approach 1:
The gate plug acts as a buffer zone that decouples the alignment requirements between contact electrodes and gate electrodes. By using a different material composition for the gate plug, the patent creates a tolerance buffer that prevents direct material interaction even when alignment tolerances are tight, thus reducing defects caused by misalignment
Solution Approach 2:
The gate plug region is given a different material composition than the surrounding contact electrode material. This local differentiation creates a chemical and physical barrier that is specifically tailored to prevent material deposition in the gate plug region, addressing the local defect problem without requiring global process changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces transistor gate short defects by isolating gate and contact electrode materials, preventing material removal errors and enhancing fabrication precision.
Implementation Method 1
depositing an electrically insulative material to fill regions between the individual lines
Implementation Method 2
using a second electrically insulative material with a different composition for the gate plug
Data Source
AI summary
Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.