3D Gate Contact Plug Layout for Stacked Memory Gate Connections
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Solution Overview
Problem
The challenge of increasing integration density in semiconductor devices is hindered by the difficulty in electrically connecting stacked gate electrodes to peripheral circuits, leading to potential defects and inefficiencies.
Innovation Solution
A semiconductor device design featuring a stack structure with alternating interlayer insulating layers and horizontal layers, including a staircase and flat regions with specific pad configurations, and gate contact plugs that penetrate through insulating regions to improve connectivity and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked gate electrodes is increased to implement high integration density, then integration density is improved, but the difficulty in electrically connecting the stacked gate electrodes to peripheral circuits increases
Solution Approach 1:
The patent transitions from planar connections to three-dimensional vertical connections by introducing stack structures with multiple tiers. Gate contact plugs are formed to extend vertically through insulating layers to electrically connect gate electrodes at different heights, enabling high-density integration while managing connection complexity through spatial dimensionality.
Solution Approach 2:
The connection structure is segmented into multiple functional components: gate contact plugs for vertical electrical connection, insulating layers for electrical isolation, and flat regions for stable plug formation. This segmentation allows each component to be optimized independently, simplifying the overall connection process despite the increased number of gate electrodes.
2Reliability
If gate contact plugs are formed in the connection region, then electrical connectivity is improved, but the manufacturing precision requirements increase due to the need for stable plug formation
Solution Approach 1:
Flat regions are formed in advance within the connection region before gate contact plug formation. These pre-prepared flat surfaces provide a stable foundation for subsequent plug deposition, ensuring consistent plug geometry and electrical connection quality. The preliminary formation of flat regions eliminates the need for complex real-time precision control during plug formation.
Solution Approach 2:
The connection region is differentiated from other regions by introducing flat regions with specific local properties. These flat regions have optimized surface characteristics that are locally tailored to receive gate contact plugs, ensuring stable plug formation without requiring high precision across the entire device structure.
3Quantity of substance
If the stack structure extends into the connection region with staircase and flat regions, then integration density is improved, but the device complexity increases
Solution Approach 1:
The stack structure is divided into distinct functional segments: staircase regions for gradual height transition and flat regions for stable connection formation. This segmentation allows the complex three-dimensional structure to be managed as discrete, manufacturable units, reducing overall device complexity while maintaining high integration density.
Solution Approach 2:
The patent utilizes vertical stacking to achieve high integration density, with gate electrodes arranged in multiple tiers along the vertical dimension. The staircase and flat regions are formed by controlling the height and position of alternating conductive and insulating layers in the vertical direction, transforming a two-dimensional layout problem into a three-dimensional solution.
Data Source
AI summary
A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.