Gate Plug Isolation Structure for Transistor Short Defect Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Transistor gate short defects occur due to material deposition in gate plug regions during patterning processes, exacerbated by alignment and critical dimension tolerances challenges in fabricating gate and contact electrodes.
Innovation Solution
The method involves forming gate electrode lines, depositing a first electrically insulative material, performing a gate cut to isolate gate electrodes, and using a second electrically insulative material with a different composition for the gate plug, which reduces the likelihood of contact electrode material deposition in the gate plug region, thereby minimizing short defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If material is deposited in gate plug region during patterning processes, then contact electrodes can be formed, but transistor gate short defects occur
Solution Approach 1:
A gate plug structure is introduced as an intermediary element between the contact electrode and the gate electrode. The gate plug is formed with a specific material composition and structure that prevents contact electrode material from directly contacting the gate electrode, thereby eliminating the short circuit defect while still allowing electrical connection through the gate plug.
Solution Approach 2:
The electrical connection path is segmented into distinct components: contact electrode, gate plug, and gate electrode. By dividing the structure into separate segments with different material compositions and formation sequences, the patent prevents unwanted material deposition and contact between the contact electrode and gate electrode, thus preventing short defects.
2Manufacturing precision
If alignment and critical dimension tolerances are reduced, then transistor features can be shrunk, but gate short defects are exacerbated
Solution Approach 1:
The gate plug is formed in advance before the contact electrode material deposition. This preliminary formation of the gate plug with appropriate dimensions and material properties creates a buffer zone that compensates for subsequent alignment variations, preventing contact electrode material from reaching the gate electrode even when alignment tolerances are tight.
Solution Approach 2:
The patent changes the material parameters and dimensional parameters of the gate plug to create a protective structure. By adjusting the gate plug's material composition, thickness, and lateral dimensions, it serves as an effective barrier against material deposition errors and alignment variations, preventing gate short defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces transistor gate short defects by allowing for the selective deposition of the gate plug material and preventing contact electrode material from entering the gate plug region, enhancing the reliability of transistor structures.
Implementation Method 1
depositing an electrically insulative material to fill regions between the individual lines
Implementation Method 2
depositing a second electrically insulative material to fill the opening, the second electrically insulative material having a different chemical composition than the first electrically insulative material
Data Source
AI summary
Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.