Gate Polysilicon Layer Segmentation for ESD and Yield
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Solution Overview
Problem
Conventional semiconductor devices face issues with the built-in resistor's small surface area leading to oxide film destruction under high voltage, unevenness between the gate pad and semiconductor substrate, and decreased yield due to etching defects.
Innovation Solution
A semiconductor device with a gate polysilicon layer having differing surface areas, connected in series between the gate pad and gate electrode, distributes voltage and reduces unevenness, enhancing electrostatic discharge (ESD) capability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a built-in resistor with small surface area is used, then the mathematical area of the cell region is prevented from being reduced, but the oxide film is destroyed under high voltage and etching defects occur
Solution Approach 1:
The gate pad is divided into two distinct portions: a first portion for wire bonding and a second portion for gate resistance connection. This segmentation allows each portion to be optimized independently, with the second portion having a smaller surface area to reduce capacitance while the overall gate pad structure maintains adequate area for reliability.
Solution Approach 2:
Different portions of the gate pad are given different surface areas tailored to their specific functions. The first portion has a larger area for robust wire bonding, while the second portion has a smaller area to minimize capacitance and prevent oxide film breakdown, achieving local optimization of both reliability and performance.
2Adaptability or versatility
If a built-in resistor with small surface area is used, then layout flexibility is improved, but unevenness between gate pad and semiconductor substrate occurs
Solution Approach 1:
The gate pad structure employs local quality differentiation where the first portion provides a larger, flatter area for wire bonding to ensure manufacturing precision, while the second portion has a smaller area optimized for electrical performance. This local optimization resolves the conflict between layout flexibility and flatness uniformity.
3Stability of the object's composition
If gate resistance is connected in series between gate pad and gate electrode, then switching operation stability is improved, but oxide film breakdown occurs due to high voltage concentration
Solution Approach 1:
The gate pad is segmented into two portions with different surface areas. The second portion's smaller area reduces capacitance and voltage concentration, preventing oxide film breakdown while the series gate resistance maintains switching stability. This segmentation resolves the contradiction between stability and reliability.
Solution Approach 2:
The surface area parameter of the gate pad portions is changed to optimize performance. By reducing the surface area of the second portion, the capacitance and voltage concentration are reduced, preventing oxide film breakdown while maintaining the stabilizing effect of the series gate resistance on switching operations.
4Productivity
If the second portion of the gate pad has smaller surface area, then capacitance is reduced for better switching performance, but ESD capability is weakened
Solution Approach 1:
The gate pad is segmented into two portions with different surface areas serving different functions. The first portion maintains adequate surface area for ESD protection, while the second portion has reduced surface area to minimize capacitance and improve switching speed, resolving the contradiction between productivity and reliability.
Solution Approach 2:
Different portions of the gate pad are given different surface areas optimized for their specific functions. The first portion provides ESD protection with adequate area, while the second portion minimizes capacitance with smaller area for fast switching, achieving local optimization that resolves the contradiction between switching speed and ESD capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses oxide film breakdown and enhances ESD capability while maintaining a stable resistance value, reducing the likelihood of etching defects and improving semiconductor device yield.
Implementation Method 1
A semiconductor device with a gate polysilicon layer having differing surface areas, connected in series between the gate pad and gate electrode, distributes voltage and reduces unevenness
Implementation Method 2
a gate polysilicon layer provided between the first main surface of the semiconductor substrate and the interlayer insulating film, the gate polysilicon layer electrically insulated from the semiconductor substrate by an oxide film
Implementation Method 3
the flow of current to MOSFET chips having a relatively low resistance value of the gate electrode is controlled. As a result, an occurrence of noise during switching of the MOSFET is suppressed
Data Source
AI summary
A gate pad includes a first portion disposed in a gate pad region and a second portion continuous with the first portion and disposed in a gate resistance region. The gate pad has a planar shape in which the second portion protrudes from the first portion. A gate polysilicon layer provided on a front surface of a semiconductor substrate via a gate insulating film is disposed between the semiconductor substrate and an interlayer insulating film, has a surface area that is at least equal to a surface area of the gate pad, and faces the gate pad in a depth direction. The gate polysilicon layer has a planar outline similar to that of the gate pad and includes continuous first and second portions, the first portion facing the first portion of the gate pad overall, and a second portion facing the second portion of the gate pad.