Gate Profile Control via Grain Size APC
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Solution Overview
Problem
Conventional IC device manufacturing lacks a method to effectively manage and control the formation of gate stacks, leading to process variations that result in gate profiles deviating from the target profile, particularly as geometry sizes decrease below 65 nanometers.
Innovation Solution
An advanced process control (APC) method is implemented, which involves forming a gate stack on a substrate through deposition, annealing, and etching processes, with real-time monitoring of grain size measurements to adjust processing recipes to achieve a target gate profile. This includes using a controller to manage and control the gate profile by modifying deposition, annealing, and etching processes based on measured grain size data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional IC device manufacturing processes are used, then production efficiency is maintained, but gate profile control deteriorates leading to process variations
Solution Approach 1:
The system performs preliminary grain size measurements after deposition and annealing processes to predict final gate profile characteristics. By measuring grain size early in the process sequence, the system can adjust subsequent etching parameters proactively rather than reactively, preventing profile deviations before they occur.
Solution Approach 2:
The APC system implements continuous feedback loops where grain size measurements from previous processes inform parameter adjustments in subsequent processes. The controller receives measurement data, compares it against target specifications, and automatically modifies deposition, annealing, or etching parameters for the next wafer or process step, creating a closed-loop control system.
2Productivity
If geometry size is scaled down below 65 nanometers, then production efficiency increases, but gate profile uniformity deteriorates
Solution Approach 1:
The system dynamically adjusts process parameters including deposition temperature, annealing temperature and time, and etching power based on measured grain size variations. By changing these parameters in response to real-time measurements, the system maintains gate profile uniformity even as feature sizes scale down to 45 nanometers and below where process variations have magnified effects.
Solution Approach 2:
The APC system applies localized parameter adjustments based on spatially-resolved grain size measurements across the wafer. Different regions of the wafer may receive different parameter modifications to compensate for local variations in grain growth, ensuring uniform gate profiles across the entire wafer surface despite scaling challenges.
3Manufacturing precision
If real-time grain size measurement and process adjustment is implemented, then gate profile control improves, but process time increases
Solution Approach 1:
The system performs grain size measurements inline or in-situ without removing wafers from the processing sequence. By integrating measurement capabilities within the existing process flow and performing measurements during or immediately after process steps, the system maintains continuous production flow while gathering necessary data for control adjustments.
Solution Approach 2:
Grain size measurements are performed at intermediate stages (after deposition and annealing) rather than waiting for complete gate stack formation. This preliminary measurement approach allows earlier detection of profile deviations and enables parameter adjustments before subsequent process steps, reducing the need for rework and minimizing overall cycle time impact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The APC method ensures that the fabricated integrated circuit devices exhibit a target gate profile, improving device performance and uniformity by dynamically adjusting process parameters to maintain grain size within a desired range, thereby addressing the challenge of process variations.
Implementation Method 1
performing a deposition process to form a gate layer over a wafer
Implementation Method 2
performing an annealing process to the gate layer based on the first grain size measurement
Data Source
AI summary
A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; performing a plurality of processes to form a gate stack over the substrate, wherein the gate stack comprises a gate layer; measuring a grain size of the gate layer after at least one of the plurality of processes; determining whether the measured grain size is within a target range; and modifying a recipe of at least one of the plurality of processes if the measured grain size of the gate layer is not within the target range.