Replacement Gate Opening Profile Tuning for Uniform Etch Back

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Solution Overview

Problem

The challenge in semiconductor manufacturing is the formation of damages such as semiconductor fin punch through during metal gate etching back processes, particularly due to non-uniform etching rates and instability, which can lead to seam voids and short circuits in gate electrodes.

Innovation Solution

The method involves tuning the profile of sacrificial gate structures by adjusting the sidewall profiles of gate openings and performing a pullback etching of spacers before depositing the work function metal layer, resulting in a more uniform and stable etching process that reduces seam voids and short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If metal gate etching back process is performed with conventional methods, then gate electrode is formed, but non-uniform etching rates cause fin punch through damages and seam voids

Engineering Contradiction:
Improveetching rate uniformityVSAvoidfin punch through damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent performs preliminary actions before the metal gate etching back process: (1) forming a sacrificial gate structure with controlled profile, (2) performing pullback etching of spacers to create an overhang, and (3) depositing work function metal layer before etching back. These preliminary steps prepare the structure to prevent fin punch through during the subsequent etching process by creating a protective overhang configuration.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes physical and chemical parameters of the etching process to achieve uniform etching rates. This includes adjusting etching conditions and using modified process parameters that account for the overhang structure, ensuring that the etching rate remains uniform throughout the gate electrode formation process, preventing both over-etching (fin punch through) and under-etching (seam voids).

Inventive Principle:
Principle #35Parameter changes

2Productivity

If etching back process is performed aggressively to remove sacrificial gate, then processing time is reduced, but seam voids and short circuits occur in gate electrodes

Engineering Contradiction:
Improveprocessing speedVSAvoidgate electrode integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent performs preliminary deposition of the work function metal layer before the etching back process. This preliminary action creates a more robust gate electrode structure that can withstand the etching back process without forming seam voids or short circuits, even when processing at optimized speeds.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The overhang structure created by the pullback etching of spacers serves as a protective cushion during the etching back process. This pre-formed overhang configuration cushions the etching process, preventing direct exposure of the fin structure and preventing seam void formation in the gate electrode, thereby maintaining reliability while enabling efficient processing.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances etching rate uniformity and stability, preventing fin damages and short circuits, thereby improving the manufacturing process of semiconductor devices.

Implementation Method 1

performing a pullback etching of spacers before depositing the work function metal layer

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

depositing the work function metal layer

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS20250366003A1Semiconductor device and method of manufacturing thereof
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250366003A1 patent drawing
  • US20250366003A1 patent drawing
  • US20250366003A1 patent drawing

AI summary

Some embodiments provide a process of tunning sidewall profiles of gate openings prior to filling a replacement gate electrode layer therein to improve etching rate uniformity and stability during a subsequent gate electrode etch back process. Particularly, the profile sacrificial gate electrode is adjusted to be more straight profile rather than a bowl type profile, which reduces the seam void created in the replacement gate electrode during the replacement gate process. In some embodiments, tuning the profile of gate opening further includes performing a pullback etching process of the sidewall spacers prior to depositing gate dielectric layer and work function metal layer to achieve a wider opening for metal gate filling in the replacement gate process.