Gate Structure Protection During Contact Formation
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Solution Overview
Problem
Conventional IC processing methods often result in over-etching of gate structures during contact formation, leading to undesirable contact resistance and degraded device performance.
Innovation Solution
A method involving the formation of an etch stop layer and a hard mask layer to protect the gate structure during contact opening formation, using chemical mechanical polishing and selective etching processes to prevent excessive etching of the gate stack, while forming contacts to both gate and doped regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional etching processes are used to form contact openings simultaneously to substrate and gate structures, then contact openings can be formed to both doped regions and gate structures, but over-etching of the gate structure occurs leading to increased contact resistance and degraded device performance
Solution Approach 1:
The patent divides the contact formation process into two separate etching operations: first forming contact openings to doped regions through the etch stop layer, then forming contact openings to gate structures through the hard mask layer. This segmentation allows independent control of each etching process, preventing over-etching of the gate structure while maintaining formation efficiency.
Solution Approach 2:
The patent introduces an etch stop layer and a hard mask layer as intermediary protective layers. The etch stop layer protects the gate structure during initial etching to doped regions, and the hard mask layer provides additional protection during subsequent etching to gate structures. These intermediaries enable precise etching control without compromising overall productivity.
2Reliability
If protective layers (etch stop layer and hard mask layer) are added to prevent over-etching of gate structures, then gate structure integrity is improved, but process complexity increases
Solution Approach 1:
The patent applies preliminary protective actions by forming the etch stop layer and hard mask layer before the etching processes. The etch stop layer is formed over the gate structure before etching to doped regions, and the hard mask layer is formed over the gate structure before etching to gate structures. This preliminary protection ensures gate integrity without requiring complex real-time control mechanisms.
Solution Approach 2:
The patent utilizes parameter changes in the form of selective etching parameters and layer thicknesses. The etch stop layer and hard mask layer have specific thicknesses and material compositions that provide the necessary protection while allowing controlled removal in subsequent steps. This approach manages complexity through well-defined parameter specifications rather than complex process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and improves device performance by preventing unwanted etching of the gate structure, thereby enhancing the reliability and efficiency of integrated circuit manufacturing.
Implementation Method 1
performing a chemical mechanical polishing (CMP) process on the first ILD and etch stop layer until a top portion of the at least one gate structure is exposed
Data Source
AI summary
Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.