Integrated Gate Protection Circuit for FET Overvoltage Discharge

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Solution Overview

Problem

Existing gate overvoltage protection circuits for power devices suffer from parasitic inductance, PCB area inefficiency, and non-zero leakage current, posing challenges for driver design and requiring high turn-on voltages.

Innovation Solution

An integrated gate protection circuit using a blocking FET and a discharge FET connected between the gate and drain of the main FET, which discharges gate charge through both FETs during fault conditions to protect the gate from excessive voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If back-to-back Zener diodes are used for gate overvoltage protection, then the gate is protected from excessive positive and negative voltages, but parasitic inductance is introduced and PCB area is increased

Engineering Contradiction:

Improvegate overvoltage protectionVSAvoidparasitic inductance

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent integrates the protection circuit directly into the power device package, merging previously separate components (Zener diodes, resistors, capacitors) into a unified integrated structure. This eliminates parasitic inductance from external connections and reduces PCB area by consolidating multiple components into a single integrated unit.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an integrated protection circuit as an intermediary between the gate and external voltage sources, using embedded Zener diodes and resistors configured to clamp gate voltage within safe limits while providing low-inductance protection paths.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If diode-connected transistors are used for overvoltage protection, then gate voltage is clamped, but non-zero leakage current flows requiring the driver to supply additional current

Engineering Contradiction:

Improveovervoltage protectionVSAvoidleakage current

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies different protection mechanisms for different voltage conditions: Zener diodes provide breakdown protection for overvoltage conditions, while diode-connected transistors provide clamping for normal operating ranges. This localized application of different protection qualities minimizes overall leakage current by only activating the higher-leakage transistor path when necessary.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the electrical parameters (voltage thresholds, resistance values) of protection components based on operating conditions, using voltage-dependent Zener breakdown characteristics for high-voltage protection and transistor threshold characteristics for normal-range clamping, optimizing the balance between protection and leakage current.

Inventive Principle:

Principle #35Parameter changes

3Area of stationary object

If protection circuits are integrated into the power device, then PCB area is reduced, but manufacturing complexity increases

Engineering Contradiction:

ImprovePCB areaVSAvoidintegration manufacturing

Core Design Contradiction:

Area of stationary objectVSEase of manufacture

Solution Approach 1:

The patent combines multiple discrete protection components (Zener diodes, resistors, capacitors, transistors) into a single integrated circuit module that is packaged together with the power device. This merging approach reduces PCB footprint by eliminating the need for separate mounting of each component while using standard integrated circuit manufacturing processes to manage production complexity.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Provides gate overvoltage protection up to 25 V, significantly higher than typical GaN FET ratings, reducing leakage current and improving driver efficiency.

Implementation Method 1

The gate protection circuit includes a blocking FET and a discharge FET connected between the gate and the drain of the main FET. The gate overvoltage protection circuit is configured to turn on both the first FET and the second FET in the event of a fault condition, such that charge from the gate of the main FET is discharged through the first FET and the second FET to the drain of the main FET

Methodology Applied

Scientific EffectField effect transistor operation:

Data Source

PatentUS12463632B2Integrated circuit for gate overvoltage protection of power devices

Publication Date: 2025.11.04 EFFICIENT POWER CONVERSION CORP

AI summary

An integrated gate overvoltage protection circuit for protecting the gate of a main field effect transistor (FET). The gate protection circuit includes a blocking FET and a discharge FET connected between the gate and the drain of the main FET. The gate overvoltage protection circuit is configured to turn on both the first FET and the second FET in the event of a fault condition, such that charge from the gate of the main FET is discharged through the first FET and the second FET to the drain of the main FET, thereby protecting the gate of the main FET.