Multi-Path Gate Pull-Down Circuit for FET Turn-Off Control

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Solution Overview

Problem

Parasitic impedances in the drive path of discrete Field Effect Transistors (FETs) in switch mode power supplies induce negative impacts on switching operations, necessitating improved control methods for efficient transistor turn-off.

Innovation Solution

A switching circuit with multiple pull-down paths and a driving circuit that modifies the pull-down strength of a transistor by adjusting the switching sequence of additional transistors based on expected turn-off modes, using pulse width modulation signals to control the transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If discrete FETs with independent gate drivers are used, then switching operation can be controlled, but parasitic impedances in the drive path induce negative impacts on switching performance

Engineering Contradiction:
Improveswitching operation reliabilityVSAvoidparasitic impedance impact
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent merges the gate driver and power transistor into a single integrated device, combining the driving circuit and power switching element into one unified structure. This integration eliminates the separate drive path that causes parasitic impedance issues, while maintaining the ability to control switching operations reliably.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an intermediate coupling structure that directly connects the gate control node to the power transistor gate, eliminating the need for separate external drive paths. This intermediary integration point removes the parasitic impedance elements that would otherwise exist in discrete configurations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple pull-down paths are added to modify turn-off characteristics, then transistor turn-off efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvetransistor turn-off efficiencyVSAvoidtransistor structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the pull-down function into multiple independent paths, each controlled by separate control signals. This allows selective activation of different pull-down paths based on operating conditions, improving turn-off efficiency while maintaining manageable complexity through modular control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of pull-down paths by using different control signals that can be selectively activated based on real-time operating conditions. This dynamic switching between pull-down paths optimizes turn-off performance without requiring all paths to be permanently active, balancing performance with complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12597921B2Switching circuit with a transistor having multiple pull down paths
Publication Date: 2026.04.07 MONOLITHIC POWER SYSTEMS INC
  • US12597921B2 patent drawing
  • US12597921B2 patent drawing
  • US12597921B2 patent drawing

AI summary

A switching circuit has a first die and a second die. The first die has a first transistor, a second transistor, and a third transistor. The second die has a fourth transistor and a driving circuit. The second transistor and the third transistor are coupled to the first transistor to provide multiple pull down paths for the first transistor. The driving circuit provides a first driving signal to control the first transistor, a second driving signal to control the fourth transistor, a first pull down control signal to control the second transistor, and a second pull down control signal to control the third transistor based on the pulse width modulation signal. A pull down strength of the first transistor is modified via the second transistor and the third transistor based on an expected turn-off mode of the first transistor.