Gate Pulse Modulating Circuit for LCD Feed-Through Reduction

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Solution Overview

Problem

Existing gate pulse modulating circuits for LCD panels face challenges in reducing the feed-through phenomenon while maintaining efficient charging of video voltage, as higher high gate voltage speeds up charging but worsens feed-through, and current solutions that use gate pulses with cutting edges consume more energy, especially in half-source driving structures.

Innovation Solution

A gate pulse modulating circuit that generates a high gate voltage with a waveform including multiple cutting edges, utilizing a timing controller, high gate voltage generating unit, and gate driver to produce gate pulses with multiple cutting edges, dividing the voltage drop into stages to reduce feed-through and energy consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If higher high gate voltage is used to speed up charging of video voltage, then charging efficiency is improved, but feed-through phenomenon becomes more serious

Engineering Contradiction:
Improvecharging efficiencyVSAvoidfeed-through phenomenon
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The gate pulse waveform is segmented into multiple stages with different voltage levels. Instead of a single high gate voltage level, the circuit uses multiple cutting edges that create staged voltage drops (e.g., from VGH to first intermediate voltage, then to second intermediate voltage, and finally to VGL). This segmentation allows the charging process to occur in controlled stages, reducing the instantaneous voltage change that causes feed-through while maintaining overall charging efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the voltage parameter dynamically during the gate pulse duration. By introducing multiple cutting edges that create staged voltage transitions, the gate voltage parameter varies over time rather than remaining constant. This parameter change strategy allows the system to achieve both fast charging (through high initial voltage) and reduced feed-through (through controlled voltage reduction at specific timings).

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If gate pulse with cutting edge waveform is generated to reduce feed-through phenomenon, then feed-through is reduced, but energy consumption increases

Engineering Contradiction:
Improvefeed-through phenomenonVSAvoidenergy consumption
Core Design Contradiction:
Object-generated harmful factorsVSUse of energy by moving object

Solution Approach 1:

The energy consumption issue is addressed by segmenting the voltage drop into controlled stages rather than a single abrupt transition. The multiple cutting edges create intermediate voltage states that allow for more efficient energy utilization. By maintaining video voltage on source lines at appropriate levels during the staged transition, the circuit reduces unnecessary energy dissipation while still achieving feed-through reduction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit performs preliminary actions by pre-charging or maintaining video voltage on source lines before the gate pulse transition. This preliminary preparation ensures that when the gate voltage transitions occur (with multiple cutting edges), the energy required to maintain proper voltage levels is minimized. The timing controller coordinates these preliminary actions with the gate pulse generation to optimize energy efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8542226B2Gate pulse modulating circuit and method
Publication Date: 2013.09.24 AU OPTRONICS CORP
  • US8542226B2 patent drawing
  • US8542226B2 patent drawing
  • US8542226B2 patent drawing

AI summary

A gate pulse modulating circuit includes a timing controller capable of generating an output enable signal and a plurality of timing control signals; a high gate voltage generating unit, electrically connected to the timing controller for receiving the timing control signals, capable of generating a high gate voltage with a waveform including a plurality of cutting edges in response to the timing control signals; a low gate voltage generating unit capable of generating a low gate voltage; and a gate driver, electrically connected to the timing controller for receiving the output enable signal and the high gate voltage generating unit for receiving the high gate voltage and the low gate voltage generating unit for receiving the low gate voltage, capable of generating a plurality of gate pulses in response to a plurality of enable periods of the output enable signal; wherein a waveform of the gate pulses includes a plurality of cutting edges.