Gate Pulse Modulation for LCD Kickback Voltage Reduction
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Solution Overview
Problem
Active matrix LCDs face issues with kickback voltage (ΔVp) due to parasitic capacitance, leading to flicker, afterimage, and color deviation, which existing gate pulse modulation methods fail to adequately address without increasing circuit complexity and power consumption.
Innovation Solution
A display device and method that modulate gate pulses by dividing a single FLK signal into multiple phases, allowing overlap of gate shift clocks while maintaining a constant timing controller configuration, using level-shifting voltages to reduce kickback voltage through synchronized FLK signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate pulse modulation is performed using a single FLK signal, then the timing controller configuration remains simple, but gate pulses that overlap each other cannot be properly modulated, failing to reduce kickback voltage effectively
Solution Approach 1:
The patent divides a single FLK signal into multiple phase-shifted FLK signals (first FLK signal, second FLK signal, etc.) using an FLK dividing circuit. Each divided FLK signal controls a corresponding gate pulse modulation circuit, enabling independent modulation of overlapping gate pulses. This segmentation allows effective kickback voltage reduction while keeping the timing controller configuration simple.
2Reliability
If gate high voltage is lowered at pulse-width duration where gate pulse is required to be maintained, then kickback voltage is reduced, but current consumption increases and data voltage charging ratio decreases
Solution Approach 1:
The patent applies gate pulse modulation only at specific local positions - the falling edges of gate pulses - rather than throughout the entire pulse-width duration. By lowering the gate high voltage only at the falling edge moment and maintaining it at normal levels during the data display period, the patent reduces kickback voltage while avoiding increased current consumption and maintaining proper data voltage charging.
3Reliability
If multiple FLK signals are generated to control overlapping gate pulses, then kickback voltage reduction is achieved, but the number of FLK signals increases adding circuits in timing controller and increasing output pins
Solution Approach 1:
The patent introduces an FLK dividing circuit as an intermediary component that receives a single FLK signal from the timing controller and divides it into multiple phase-shifted FLK signals. This intermediary approach enables effective control of overlapping gate pulses without increasing the output pin count of the timing controller or adding complex circuitry within the timing controller itself.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces kickback voltage without altering the timing controller configuration, improving display stability and reducing current consumption by modulating falling edge voltages of gate pulses.
Implementation Method 1
a gate driving circuit configured to generate gate pulses by level-shifting voltages of the gate shift clocks, to modulate falling edge voltages of the gate pulses in response to the divided FLK signals
Implementation Method 2
The LCD displays images by controlling an electric field applied to LC cells to adjust a light from a backlight
Implementation Method 3
a voltage charged in the LC cell is influenced by a kickback voltage (or a feed through voltage) ΔVp generated due to a parasitic capacitance in the TFT
Data Source
AI summary
A display device comprises a display panel in which data lines and gate lines cross each other, a timing controller which outputs a single gate pulse modulation control signal (“FLK signal”) and I-phase (where I is an integer equal to or more than 2) gate shift clocks which are sequentially delayed, an FLK dividing circuit which divides the single FLK signal to output J (where J is an integer equal to or more than 2 and smaller than I) FLK signals, a data driving circuit which converts digital video data into data voltages to supply the data voltages for the data lines, and a gate driving circuit which generates gate pulses by level-shifting voltages of the gate shift clocks, to modulate falling edge voltages of the gate pulses in response to the divided FLK signals, and to sequentially supply the modulated gate pulses for the gate lines.