Gate Pulse Waveform Control for LCD Power and Kickback Reduction
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Solution Overview
Problem
Active matrix LCDs face issues with high power consumption and kickback voltage, which cause flickers and afterimages in displayed images due to parasitic capacitance, and existing gate pulse modulation methods are limited in reducing these issues.
Innovation Solution
A display device and method that control gate pulses by increasing voltage from a gate low voltage to a precharging voltage during a first rising time, then to a gate high voltage during a second rising time, and decrease voltage from the gate high voltage to the precharging voltage during a first falling time, and finally to the gate low voltage during a second falling time, using a power sharing level shifter to reduce power consumption and kickback voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate pulses rapidly switch between gate low voltage and gate high voltage, then switching speed is improved, but power consumption increases and kickback voltage is generated
Solution Approach 1:
The gate pulse waveform is segmented into multiple stages: a first gradual transition phase from gate low voltage to gate high voltage, and a second rapid transition phase. This segmentation allows the pulse to maintain fast switching capability while reducing the overall power consumption by distributing the voltage transition over time, thereby reducing instantaneous current spikes and associated power loss.
Solution Approach 2:
A precharging phase is introduced before the main switching action. The gate voltage is precharged to an intermediate level before the final transition to gate high voltage. This preliminary action reduces the voltage difference that must be overcome during the main switching event, thereby reducing the kickback voltage generated by parasitic capacitance and lowering overall power consumption.
2Speed
If gate pulses rapidly switch between gate low voltage and gate high voltage, then switching speed is improved, but kickback voltage increases causing display defects
Solution Approach 1:
The gate pulse waveform is segmented into multiple stages: a first gradual transition phase from gate low voltage to gate high voltage, and a second rapid transition phase. This segmentation allows the pulse to maintain fast switching capability while reducing the overall power consumption by distributing the voltage transition over time, thereby reducing instantaneous current spikes and associated power loss.
Solution Approach 2:
A precharging phase is introduced before the main switching action. The gate voltage is precharged to an intermediate level before the final transition to gate high voltage. This preliminary action reduces the voltage difference that must be overcome during the main switching event, thereby reducing the kickback voltage generated by parasitic capacitance and lowering overall power consumption.
3Object-generated harmful factors
If existing gate pulse modulation methods are used to reduce kickback voltage, then kickback voltage is reduced, but power consumption is not effectively reduced
Solution Approach 1:
The gate pulse waveform dynamically adjusts its transition characteristics by incorporating both gradual and rapid transition phases. The first phase uses a gradual transition to minimize kickback voltage, while the second phase provides rapid switching when needed. This dynamic waveform structure simultaneously addresses both kickback voltage reduction and power consumption optimization, overcoming the limitation of existing modulation methods that only addressed kickback voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power consumption and kickback voltage, minimizing flickers and afterimages in displayed images while maintaining efficient operation of the LCD.
Implementation Method 1
The kickback voltage (or feed through voltage, ΔVp) generated due to the parasitic capacitance of the TFT
Data Source
AI summary
A display device comprises a display panel including data lines and gate lines crossing each other, a data driving circuit configured to convert digital video data into data voltages which are supplied to the data lines, a gate driving circuit configured to sequentially supply gate pulses to the gate lines, wherein a voltage of each of the gate pulses increases from a gate low voltage to a precharging voltage during a first rising time and thereafter increases from the precharging voltage to a gate high voltage during a second rising time, and wherein the voltage of each of the gate pulses decreases from the gate high voltage to the precharging voltage during a first falling time and thereafter decreases from the precharging voltage to the gate low voltage during a second falling time.


