Power Transistor Gate Pulsing for Capacitive Load Inrush Control
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Solution Overview
Problem
Existing methods for charging high-capacitive loads in electrical circuits face challenges in efficiently powering capacitive loads without causing thermal instability in power transistors or triggering short circuits, while maintaining a safe current density.
Innovation Solution
A method involving a control circuit that applies first and second pulse signals to the gate of a power transistor, with rest periods, and monitors voltage and current levels to adjust the pulse frequency and duration, ensuring the power transistor remains within thermal stability zones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single long pulse signal is applied to the gate of the power transistor, then the capacitive load can be charged, but the inrush current causes voltage dips and may damage components
Solution Approach 1:
The patent divides the single long pulse signal into multiple shorter pulse signals with rest periods in between. This segmentation allows the capacitive load to charge in steps, preventing the excessive inrush current that would occur with a single long pulse, thereby avoiding voltage dips and protecting components while still achieving full charging of the capacitor.
Solution Approach 2:
The patent employs periodic pulse signals with alternating active periods (charging) and rest periods (stabilization). This periodic action allows the system to charge the capacitive load in controlled intervals, preventing continuous high current flow that causes voltage dips, while ensuring the load is fully charged over time through repeated cycles.
2Object-affected harmful factors
If multiple pulse signals with rest periods are applied to charge the capacitive load, then inrush current is reduced, but the switching time increases
Solution Approach 1:
The patent uses feedback mechanisms (such as voltage detection circuits or current sensing) to monitor the charging state of the capacitive load during the pulse sequence. Based on this feedback, the control circuit can dynamically adjust the pulse width, rest period duration, or number of pulses required, optimizing the charging process to minimize total switching time while maintaining safe current levels that prevent inrush current damage.
3Productivity
If the pulse width is increased to charge large capacitive loads faster, then productivity improves, but the risk of component damage due to inrush current increases
Solution Approach 1:
The patent implements dynamic pulse width modulation where the width and amplitude of pulse signals are adjusted in real-time based on the charging state of the capacitive load. This allows the system to apply wider pulses when the capacitor is partially charged (when it can accept higher current), and reduce pulse width as the capacitor approaches full charge, thereby maximizing charging speed while preventing inrush current from damaging components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows rapid charging of capacitive loads while preventing thermal instability and short circuits, maintaining the power transistor's safety and efficiency.
Implementation Method 1
a capacitive load (104) of the circuit
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
The present description relates to a method comprising: - the application, by a control circuit (206), of a first pulse signal, consisting of first consecutive voltage pulses, to the gate of a power transistor (202) supplying a capacitive load of the circuit (104), the pulses of the first pulse signal being separated by a first rest period; - following one or more of the pulses of the first signal, a comparison, by a comparator (212), of the value of the voltage (VbatA) across the capacitive load with a first threshold voltage value (Vout_th); and - if the first threshold voltage value is exceeded, the application of a second pulse signal, consisting of second consecutive voltage pulses, to the gate of the power transistor, the pulses of the second pulse signal being separated by a second rest period shorter than the first rest period.