Replacement Gate Dielectric Recessing to Suppress CMP Dishing
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Solution Overview
Problem
The semiconductor industry faces challenges in suppressing dishing problems during chemical mechanical polishing (CMP) operations in gate replacement technologies for FinFET devices, which affect the isolation properties of the cap insulating layer and increase manufacturing costs.
Innovation Solution
A method is introduced that involves multiple dielectric layer formations and controlled CMP processes to effectively planarize and recess the sacrificial gate structures, including the use of silicon oxide and silicon nitride-based materials, with specific CMP operations and end-point detection techniques to minimize dishing and improve the isolation properties of the cap insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) operations are performed during gate replacement technology, then planarization is achieved, but dishing problems occur that affect isolation properties and increase manufacturing costs
Solution Approach 1:
The patent divides the gate electrode structure into multiple segments by forming recesses at different levels. The gate electrode is segmented such that portions are recessed to different depths, creating a multi-level structure that prevents dishing during CMP operations while maintaining proper electrical isolation.
Solution Approach 2:
The patent performs preliminary recessing of the gate electrode structure before final CMP operations. By pre-forming recesses and removing material in controlled steps prior to the main planarization process, the structure is prepared to resist dishing effects during subsequent CMP steps.
2Productivity
If gate replacement technology is used for FinFET devices, then device density and performance are improved, but dishing problems during CMP increase manufacturing complexity and costs
Solution Approach 1:
The gate electrode is divided into multiple recessed levels, segmenting the structure to prevent dishing. This segmentation approach maintains the high device density benefits of gate replacement technology while simplifying the CMP process by preventing the formation of dished surfaces that would require additional corrective steps.
Solution Approach 2:
Different portions of the gate electrode structure are given different local qualities through selective recessing. Areas prone to dishing are recessed to different depths, creating local variations in the structure that prevent uniform dishing across the entire gate area, thereby reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses dishing problems, enhances the isolation properties of the cap insulating layer, and reduces manufacturing costs by optimizing the planarization and recessing processes in the gate replacement technology.
Implementation Method 1
chemical mechanical polishing (CMP) operations
Data Source
AI summary
In a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed while a lower portion of the sacrificial gate structure is embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed.