Gate Refill Metal Dielectric Liner for GAA Isolation Reliability

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Solution Overview

Problem

As the scale of fin width in fin field effect transistors (FinFETs) decreases, channel width variations can cause mobility loss, and in GAA transistors, reducing gate-to-gate pitch by forming thinner gate spacers increases the risk of isolation breakdown between the metal gate and source/drain contact.

Innovation Solution

An additional dielectric liner is formed before the gate refill metal is deposited, increasing the distance between the gate refill metal and the source/drain contact, thereby reducing the risk of isolation breakdown.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If gate spacers are made thinner to reduce gate-to-gate pitch in GAA transistors, then device integration density is improved, but the risk of isolation breakdown between metal gate and source/drain contact increases

Engineering Contradiction:
Improvedevice integration densityVSAvoidisolation breakdown risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A dielectric liner is introduced as an intermediary layer between the gate refill metal and the source/drain contact. This liner acts as a protective barrier that prevents direct contact and potential breakdown, while allowing the gate spacer thickness to be reduced for higher integration density. The dielectric liner effectively mediates the interaction between the metal gate and source/drain regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric liner is formed beforehand before depositing the gate refill metal, creating a protective cushion layer in advance. This pre-formed liner provides isolation protection before the metal gate structure is completed, preventing potential breakdown paths from forming during subsequent processing steps.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If additional dielectric liner is formed before gate refill metal deposition, then isolation reliability is improved, but device complexity increases

Engineering Contradiction:
Improveisolation breakdown riskVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dielectric liner is formed as a preliminary step before gate refill metal deposition. By performing this isolation-enhancing action early in the gate formation sequence, the subsequent metal deposition and patterning steps become simpler and more reliable, as the liner is already in place to guide and protect the process.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12243918B2Semiconductor device with dielectric liners on gate refill metal
Publication Date: 2025.03.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12243918B2 patent drawing
  • US12243918B2 patent drawing
  • US12243918B2 patent drawing

AI summary

A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first di electric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.