Gate Dielectric Relaxation Anneal for Interface Defect Reduction
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Solution Overview
Problem
Carrier mobility in transistors is limited due to defects and fixed charge at the gate dielectric-silicon interface, which are exacerbated by the rapid temperature ramp rates in dynamic surface annealing processes, making it difficult to improve without altering the high ramp rates necessary for dopant profile preservation.
Innovation Solution
A pre-implant relaxation anneal step is introduced, where the substrate temperature is slowly ramped up to and down from the silicon melting temperature at rates less than 250 degrees C. per second, allowing for defect repair and minimizing fixed charge in the gate dielectric, thereby improving carrier mobility without affecting the dopant profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dynamic surface annealing with high temperature ramp rates is used to activate implanted dopants, then dopant profile integrity is maintained, but defect density and fixed charge increase at the gate dielectric-silicon interface
Solution Approach 1:
A pre-implant relaxation anneal step is performed before ion implantation to repair defects in the gate dielectric-silicon interface. This preliminary action prepares the interface by slowly ramping the temperature up and down (less than 250 degrees C. per second), allowing defects to be annealed or cured before the dopant implantation and subsequent high-rate dynamic surface annealing process
Solution Approach 2:
The temperature ramping process is segmented into two distinct phases: a slow relaxation anneal phase (less than 250 degrees C. per second) performed before ion implantation to repair interface defects, and a fast dynamic surface annealing phase (million degrees C. per second) performed after ion implantation to activate dopants while preserving the repaired interface
2Reliability
If high temperature ramp rates are used in dynamic surface annealing, then dopant diffusion is prevented, but carrier mobility deteriorates due to fixed charge at the interface
Solution Approach 1:
The pre-implant relaxation anneal step is performed as a preliminary action before ion implantation to reduce fixed charge and repair interface defects. This allows the subsequent high-rate dynamic surface annealing to proceed without degrading carrier mobility, as the interface has already been prepared and stabilized
Solution Approach 2:
The temperature ramp rate parameter is changed based on the process stage: slow ramp rates (less than 250 degrees C. per second) are used during the pre-implant relaxation anneal to allow defect repair, while fast ramp rates (million degrees C. per second) are used during post-implant dynamic surface annealing to activate dopants without causing additional interface damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces defect density and fixed charge at the gate dielectric-silicon interface, enhancing carrier mobility in the source-drain channel while maintaining the high ramp rates required for dopant profile integrity.
Implementation Method 1
performing millisecond laser annealing by scanning a laser-generated light beam across the substrate so as to rapidly raise each region illuminated by the beam to a peak temperature at or near the melting temperature of the material of the semiconductor substrate
Implementation Method 2
rapidly cool it by conduction to the surrounding material
Implementation Method 3
a gate dielectric relaxation annealing step is performed by raising the temperature of the substrate from an ambient temperature to the peak temperature of the millisecond laser annealing at a first rate and decreasing the temperature of the substrate from the peak temperature to an ambient temperature at a second rate, the first and second rates being less than 250 degrees C. per second
Data Source
AI summary
Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.