Gate Resistance Adjustment for Power Semiconductor Surge Control

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Solution Overview

Problem

The optimization of gate resistance in power semiconductor devices is currently reliant on trial and error and lacks a theoretical method, leading to inefficiencies in reducing surge voltage while managing switching loss.

Innovation Solution

A gate resistance adjustment device that inputs waveforms of drain or collector voltage and current, extracts relevant times and steady-state currents, calculates optimal gate resistance using model equations based on electrical characteristics, and sets the resistance accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If gate resistance is increased to reduce surge voltage, then surge voltage is reduced, but turn-on time and turn-off time increase resulting in increased switching loss

Engineering Contradiction:
Improvesurge voltageVSAvoidswitching loss
Core Design Contradiction:
Object-affected harmful factorsVSLoss of energy

Solution Approach 1:

The patent applies dynamics by making the gate resistance adjustable rather than fixed. The resistance value can be dynamically changed based on operating conditions, allowing optimization of both surge voltage suppression and switching speed for different scenarios. This resolves the contradiction by enabling the system to adapt between the two opposing requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of gate resistance from a fixed value to a variable that can be adjusted. By modifying the resistance parameter according to specific operating conditions, the patent achieves optimal performance in both surge voltage reduction and switching loss minimization, resolving the trade-off between these two parameters.

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If gate resistance is decreased to reduce switching loss, then turn-on time and turn-off time are reduced, but the power semiconductor device becomes more susceptible to surge voltage

Engineering Contradiction:
Improveswitching lossVSAvoidsurge voltage susceptibility
Core Design Contradiction:
Loss of energyVSObject-affected harmful factors

Solution Approach 1:

The adjustable gate resistance allows the system to dynamically switch between low resistance (for fast switching and reduced loss) and high resistance (for surge protection) based on real-time operating conditions, resolving the contradiction between switching performance and surge immunity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

By making the gate resistance parameter adjustable, the patent enables optimization of switching loss through lower resistance values while maintaining surge protection capability through higher resistance values when needed, thus resolving the trade-off between these conflicting requirements.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If gate resistance is adjusted by trial and error, then optimization may be achieved, but the process takes a lot of time and relies on designer experience

Engineering Contradiction:
Improvegate resistance optimizationVSAvoidadjustment time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent incorporates feedback mechanisms that automatically monitor and adjust gate resistance based on measured performance parameters. This eliminates the need for manual trial-and-error adjustment by designers, significantly reducing optimization time while maintaining or improving the reliability of gate resistance selection.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs self-adjustment of gate resistance based on predefined criteria and real-time measurements, without requiring external designer intervention. This automated self-service approach eliminates time-consuming manual optimization while ensuring reliable gate resistance values are used.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11658653B2Gate resistance adjustment device
Publication Date: 2023.05.23 KK TOSHIBA
  • US11658653B2 patent drawing
  • US11658653B2 patent drawing
  • US11658653B2 patent drawing

AI summary

A gate resistance adjustment device has a waveform input unit that inputs waveforms of a drain voltage or a collector voltage and a drain current or a collector current at least one of during which a switching device is turned on and during which the switching device is turned off, an extraction unit that extracts time required for at least one of turning on or off the switching device and a steady-state drain current or a steady-state collector current of the switching device based on the waveforms input by the waveform input unit, a calculator that calculates a gate resistance of the switching device based on the time and the steady-state drain current or the steady-state collector current that are extracted by the extraction unit, and a setting unit that sets a gate resistance calculated by the calculator in the switching device.