Gate-Based Resistance Control Units for Neural Network Weight Storage
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Solution Overview
Problem
Analog-based resistive processing units for neural networks face data retention issues due to leakage current and resistance drifting, leading to unreliable weight values and increased circuit layout area and fabrication costs.
Innovation Solution
The implementation of a resistance control unit in a neural network formed on an integrated circuit, comprising gate-based resistors, switches, and memory cells, which allows for reliable resistive memory computing by controlling current flow and providing a controllable resistor for weight values, reducing routing area and fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If analog-based resistive processing units are used for neural networks, then processing speed is improved, but data retention reliability deteriorates due to leakage current and resistance drifting
Solution Approach 1:
The patent segments the resistive processing unit into multiple independent storage elements (e.g., 6T-SRAM cells) that digitally store weight values, separating the weight storage function from the computational function. This segmentation allows digital storage elements to maintain reliable data retention while analog computing elements perform fast processing operations.
Solution Approach 2:
The patent introduces digital-to-analog conversion elements (e.g., resistor networks controlled by switch arrays) as intermediaries between digital storage elements and analog computing elements. These intermediaries translate digital weight values into analog conductance values, enabling reliable digital storage to support fast analog processing without direct exposure to leakage and drift issues.
2Speed
If analog-based resistive processing units are used, then processing speed is improved, but circuit layout area increases
Solution Approach 1:
The patent designs storage elements (e.g., 6T-SRAM cells) that serve multiple functions: they store weight values digitally, provide address decoding, and control the analog computing operations through integrated switch arrays. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall circuit layout area while maintaining fast processing speed.
3Speed
If analog-based resistive processing units are used, then processing speed is improved, but fabrication cost increases
Solution Approach 1:
The patent utilizes standard CMOS fabrication processes to create resistive processing units, changing the manufacturing parameters from specialized analog processes to conventional digital CMOS processes. This approach reduces fabrication costs by leveraging existing, well-established manufacturing infrastructure while maintaining fast analog processing capabilities through careful circuit design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a reliable and efficient resistive memory system for neural networks, improving data retention and reducing processing difficulties and fabrication costs by using a combination of resistors, switches, and memory cells to control current flow and weight values.
Implementation Method 1
Each of the plurality of gate structures includes a gate electrode, a first source region, and a first drain region
Implementation Method 2
analog weight update. First, these analog based accelerator devices would incur data retention issue due to leakage current and resistance drifting
Data Source
AI summary
Disclosed are resistance control units based on gates, switches and/or memory cells. In one embodiment, a resistance control unit of a neural network formed on an integrated circuit (IC) is disclosed. The resistance control unit includes: a plurality of resistors coupled between a first node and a second node of the neural network; a plurality of switches coupled to the plurality of resistors and configured for controlling a current flowing from the first node to the second node; and a plurality of memory cells configured for generating a digital output. The plurality of switches can be controlled by the digital output.