Built-In Gate Resistance Trenches for Adjustable MOSFET Gate Control
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Solution Overview
Problem
Conventional semiconductor devices with built-in gate resistors face challenges in easily adjusting the resistance value of the gate electrode, requiring multiple pattern changes and being susceptible to stress from thermal oxide films, making it difficult to control the switching speed of switching elements like IGBTs and MOSFETs.
Innovation Solution
The semiconductor device incorporates a built-in gate resistance region with multiple parallel trenches connected between the gate wiring and pad, allowing for adjustment of the resistance value by varying the number of trenches and inter-contact distance, using a CVD interlayer film to reduce stress and improve adjustability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a trench type built-in gate resistor is connected to a gate electrode with polysilicon wiring, then the gate electrode can be electrically connected, but it requires changing multiple patterns (trench, polysilicon wiring, contact) to control resistance value, making it difficult to adjust
Solution Approach 1:
The built-in gate resistance region is divided into multiple partial built-in gate resistance regions (first, second, third, fourth regions) that are connected in parallel between the gate wiring and gate pad. Each partial region can be independently adjusted by controlling the number of built-in gate resistance trenches, allowing flexible resistance value adjustment without changing multiple patterns.
Solution Approach 2:
The resistance value is made dynamically adjustable by varying the number of built-in gate resistance trenches in each partial region. By controlling the trench formation conditions (such as etching depth or trench width), the resistance value can be optimized for different applications without requiring multiple mask patterns.
2Reliability
If a thermal oxide film with relatively large film thickness is provided around the built-in gate resistance region, then the region is protected, but stress is likely to be applied to the built-in gate resistance region
Solution Approach 1:
The film thickness of the interlayer insulating film is optimized to a specific range (50 nm to 200 nm) that balances protection and stress reduction. This parameter optimization ensures the built-in gate resistance region is sufficiently protected while minimizing stress application, resolving the contradiction between protection and stress.
3Ease of manufacture
If multiple patterns (trench, polysilicon wiring, contact) are used to control resistance value, then electrical connection is achieved, but the resistance value is not easy to adjust due to need to prepare multiple masks
Solution Approach 1:
The gate wiring, built-in gate resistance regions, and gate pad are integrated into a unified structure where the built-in gate resistance trenches are directly formed in the semiconductor substrate between the gate wiring and gate pad. This merging eliminates the need for separate polysilicon wiring and contact patterns, allowing resistance value adjustment through a single trench formation process.
Data Source
AI summary
All of four of built-in gate resistance trenches function as practical built-in gate resistance trenches. A first end portion of each of four of the built-in gate resistance trenches is electrically connected to a wiring side contact region of a gate wiring via a wiring contact. A second end portion of each of four of the built-in gate resistance trenches is electrically connected to a pad side contact region of a gate pad via a pad contact. In each of four of the built-in gate resistance trenches, a distance between the wiring contact and the pad contact is defined as an inter-contact distance.