Gate Resistor Layout Using Multilayer Wiring in Semiconductor Devices
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Solution Overview
Problem
The use of low-resistance metallic materials for gate electrodes in transistors leads to increased layout area of resistive elements, necessitating innovative configurations to maintain desired resistance values while minimizing layout area and enhancing transistor operation speed.
Innovation Solution
The semiconductor device incorporates a gate resistive element with a meandering or spiral configuration, utilizing elongate and connecting members made of low-resistance materials, integrated with multi-layered wiring layers to achieve desired resistance values while reducing layout area, and optionally employing silicon nitride films to increase sheet resistance and reduce layout area further.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low-resistance metallic materials are used for gate electrodes, then transistor operation speed is improved, but layout area of resistive elements increases
Solution Approach 1:
The patent transitions from planar resistive element configurations to three-dimensional multi-layered wiring structures. By stacking multiple wiring layers vertically and using via holes to connect them, the resistive element utilizes the third dimension (height) to achieve the desired resistance value within a smaller footprint area, thereby resolving the contradiction between speed improvement and area increase
Solution Approach 2:
The patent embeds multiple wiring layers within each other in a vertical stack, with lower wiring layers nested inside the structure of upper layers. This nesting approach allows multiple conductive paths to occupy overlapping horizontal space at different vertical levels, effectively reducing the total layout area while maintaining the electrical functionality required for high-speed operation
Data Source
AI summary
A semiconductor device includes a transistor including a first metallic-layer as a gate electrode above a front face of a substrate. A first wiring layer includes first to third elongate members constituted of the same material as the first metallic layer and extending in a first direction, and first and second connecting members constituted of the same material as the first metallic layer, extending in a second direction, and connecting the first to third elongate members. A second wiring layer is provided above the first metallic layer, and includes fourth to sixth elongate members extending in the first or second direction, and third and fourth connecting members constituted of the same material as that of the fourth to sixth elongate members, extending in the other of the first and second directions, and connecting the fourth to sixth elongate members. The first and second wiring layers are connected to each other.