Gate rounding reduces MOSFET leakage current
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Solution Overview
Problem
Metal oxide semiconductor field effect transistors (MOSFETs) experience significant leakage current, leading to static power consumption and heat generation, especially in smaller devices, which existing techniques like high-threshold and long-channel designs attempt to mitigate but at increased cost and area requirements.
Innovation Solution
The gate-rounding technique involves depositing polysilicon gate tips with rounded junctions to the main gate region, increasing the effective channel length and reducing leakage current by forming gate-rounded regions that cover parts of the substrate, thereby decreasing static power consumption without increasing the transistor's area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-threshold or long-channel designs are used to reduce leakage current, then leakage current is reduced, but fabrication cost and device area increase
Solution Approach 1:
The patent applies gate rounding at the corners of the gate structure, transforming sharp corners into curved surfaces. This curvature modifies the electric field distribution at the gate-substrate interface, reducing peak field intensity and thereby decreasing leakage current without requiring long-channel or high-threshold designs, avoiding increased fabrication cost
2Loss of energy
If high-threshold or long-channel designs are used to reduce leakage current, then leakage current is reduced, but device area increases
Solution Approach 1:
By rounding the gate corners with a specific radius, the patent reduces leakage current through modified electric field distribution while maintaining the same device footprint. The curvature effect achieves leakage reduction without extending the channel length or increasing device area
3Loss of energy
If gate rounding is applied to reduce leakage current, then leakage current is reduced, but gate structure complexity increases
Solution Approach 1:
The gate rounding is implemented as a simple geometric modification to existing gate structures. The rounded corners are formed through standard fabrication processes such as anisotropic etching or selective oxidation, adding minimal complexity while effectively reducing leakage current
Data Source
AI summary
Gate-rounding fabrication techniques can be implemented to increase an effective channel length of a transistor and to consequently reduce the leakage current and static power consumption associated with the transistor. The transistor comprises a substrate region that includes a source region and a drain region. The transistor can also comprise a gate region that includes a main gate portion, one or more gate tips, and one or more corresponding gate-rounded portions. Each of the one or more gate tips is formed at a suitable position along the side of the main gate portion. During fabrication, the junction between the main gate region and each of the gate tips takes on a rounded shape to form a corresponding gate-rounded region. The gate-rounded regions increase the average length of the gate region and the effective channel length of the transistor.