Gate Runner Resistivity Gradient for Soft Switching
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Solution Overview
Problem
Transistor devices with wide bandgap semiconductor materials face high voltage spikes due to rapid changes in load current, which is undesirable and requires a soft switching behavior to mitigate these spikes.
Innovation Solution
The transistor device incorporates gate runners with increasing resistivity per area along their longitudinal direction, which delays the switching time of transistor cells connected to them, thereby reducing the gradient of on-resistance and achieving soft switching behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the transistor device switches on and off rapidly to improve switching speed, then the productivity is improved, but voltage spikes increase due to high load current gradient
Solution Approach 1:
The gate runner is designed with non-uniform resistivity distribution, where the resistivity per area increases in the longitudinal direction from the gate pad. This local variation in electrical properties creates different delay times for different transistor cells, softening the switching behavior and reducing voltage spikes while maintaining acceptable switching speed.
Solution Approach 2:
The patent changes the electrical resistance parameter of the gate runner by creating a resistivity gradient. The resistivity per area is varied along the longitudinal direction, which directly affects the delay time of transistor cells and enables soft switching to reduce voltage spikes.
2Object-affected harmful factors
If the resistivity per area of gate runners is increased to reduce voltage spikes, then the harmful factors are reduced, but the switching speed decreases
Solution Approach 1:
Instead of uniformly increasing resistivity throughout the gate runner, the patent applies increased resistivity selectively in specific regions. The resistivity per area increases in the longitudinal direction but maintains lower values near the gate pad, creating localized delay effects that reduce voltage spikes without significantly impacting overall switching speed.
Solution Approach 2:
The patent applies partial action by increasing resistivity only in certain sections of the gate runner rather than throughout the entire structure. This selective application of increased resistivity provides enough delay to reduce voltage spikes while minimizing the impact on switching speed.
3Productivity
If all transistor cells switch simultaneously to maintain fast response, then the productivity is improved, but voltage spikes increase due to simultaneous current change
Solution Approach 1:
The gate runner is designed with spatially varying resistivity properties, where different regions have different resistivity per area. This causes transistor cells at different positions along the gate runner to experience different delay times, resulting in sequential switching rather than simultaneous switching, thereby reducing voltage spikes.
Solution Approach 2:
The resistivity gradient in the gate runner creates preliminary delay effects that stagger the switching of transistor cells. By the time the switching signal reaches transistor cells further along the gate runner, the earlier cells have already begun switching, which softens the overall current transition and reduces voltage spikes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces voltage spikes by increasing the delay time between the switching of individual transistor cells, resulting in a smoother transition and lower voltage levels during state changes.
Implementation Method 1
At least one gate runner of the plurality of gate runners comprises at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases
Data Source
AI summary
In an example, a transistor device is provided. The transistor device includes a plurality of transistor cells each including a gate electrode and each at least partially integrated in a semiconductor body that includes a wide bandgap semiconductor material. The transistor device includes a gate pad arranged on top of the semiconductor body, and a plurality of gate runners each arranged on top of the semiconductor body and each connected to gate electrodes of at least some of the plurality of transistor cells. Each gate runner of the plurality of gate runners has a longitudinal direction, and at least one of the gate runners includes at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.