Gate Runner Contact Layout for Uniform Gate Signal Timing

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Solution Overview

Problem

Existing semiconductor devices face challenges in maintaining reliability due to variations in timing of gate signal transmission across unit cells, which can lead to inefficiencies and reduced performance.

Innovation Solution

The semiconductor device design includes a gate contact region formed in a partial region of the gate runner, with optimized distances between gate runners and contact points to minimize timing differences in gate signal transmission, ensuring uniform signal delivery across unit cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If gate runners are extended to cover the entire gate frame, then signal distribution coverage is improved, but timing variations in gate signal transmission increase

Engineering Contradiction:
Improvegate runner coverage areaVSAvoidgate signal transmission timing consistency
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent extracts the gate contact region from the gate runner structure, forming a separate integrated contact structure. This allows the gate runner to be shortened and repositioned such that its end overlaps with the gate frame above the active region, while the gate contact region provides the actual electrical connection. This separation resolves the contradiction by eliminating the need for extensive gate runner coverage while maintaining reliable, timely signal transmission to all unit cells.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The gate contact region acts as an intermediary between the gate runner and the gate frame/unit cells. Instead of the gate runner directly covering and connecting to all areas of the gate frame, the gate contact region serves as the intermediate connection point. This mediator structure enables compact gate runner placement while ensuring uniform signal distribution timing across all unit cells through optimized electrical connection geometry.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Stability of the object's composition

If gate contact regions are formed across the entire gate frame, then signal distribution uniformity is improved, but device complexity increases

Engineering Contradiction:
Improvegate signal transmission uniformityVSAvoidgate runner and contact structure complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent applies local quality by concentrating the gate contact region specifically above the active region rather than distributing it uniformly across the entire gate frame. The gate runner is positioned to overlap with the gate frame only in the regions corresponding to active unit cells, where signal transmission is needed. This localized approach maintains signal uniformity for functional areas while reducing overall structural complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The gate runner is designed to extend partially along the gate frame rather than covering the entire perimeter. The runner's end overlaps with the gate frame above the active region, providing sufficient contact for all unit cells without excessive extension. This partial action achieves the necessary signal distribution uniformity while avoiding the complexity of complete gate frame coverage.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP4712139A1Semiconductor device with gate contact region formed in partial region of gate runner
Publication Date: 2026.03.18 SAMSUNG ELECTRONICS CO LTD
  • EP4712139A1 patent drawingFigure 1
  • EP4712139A1 patent drawingFigure 2
  • EP4712139A1 patent drawingFigure 3

AI summary

A semiconductor device includes: a substrate including (i) a first active region comprising a plurality of unit cells, and (ii) a peripheral area surrounding at least a portion of the first active region; a gate frame comprising (i) a first portion in a wiring region and extending along a first direction, (ii) a second portion extending from one side of the first portion along a second direction crossing the first direction and connected to a first end of at least a portion among the plurality of unit cells, and (iii) a third portion extending from the first side along the second direction and connected to a second end of at least a portion among the plurality of unit cells; a first gate runner on the first portion of the gate frame and the second portion of the gate frame; and a second gate runner on the third portion.