Gate Seal Structure for FinFET Gate Extrusion Control
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Solution Overview
Problem
The semiconductor industry faces challenges in reliably fabricating gates around raised features in FinFETs, particularly in trenches between fins, due to defects such as metal gate extrusion and surface roughness, which affect device yield and performance.
Innovation Solution
A gate seal is formed around the placeholder gate before depositing the gate spacer, providing a barrier against extrusion and improving surface uniformity, reducing defects and enhancing the adhesion of the gate spacer, thereby improving the fabrication process and device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a placeholder gate is formed around raised fins in trenches, then the gate structure can be fabricated, but metal gate extrusion defects occur and surface roughness increases
Solution Approach 1:
A gate seal layer is introduced as an intermediary component between the placeholder gate and the gate spacer. This gate seal serves as a mediator that prevents metal gate extrusion and provides a uniform surface for subsequent spacer deposition, thereby resolving the contradiction between ease of manufacture and manufacturing precision
Solution Approach 2:
The gate seal is formed in advance before the gate spacer deposition process. This preliminary action prepares the surface beforehand to prevent extrusion defects and ensure uniformity, allowing the main gate fabrication process to proceed without defects
2Reliability
If metal is used as gate conductor instead of polysilicon, then higher conductance is achieved, but gate extrusion defects increase
Solution Approach 1:
The gate seal acts as a protective intermediary that constrains the metal gate conductor, preventing it from extruding while allowing the metal to maintain its high conductance properties. This resolves the contradiction by isolating the harmful extrusion effect from the beneficial conductance property
3Device complexity
If gate spacer is deposited directly on placeholder gate, then fabrication process is simplified, but adhesion and uniformity are compromised
Solution Approach 1:
The gate structure is segmented into distinct functional layers: placeholder gate, gate seal, and gate spacer. This segmentation allows each layer to perform its specific function - the gate seal provides a uniform surface for spacer adhesion while keeping the overall process relatively simple
Solution Approach 2:
The gate seal serves as an intermediary layer between the placeholder gate and gate spacer, improving adhesion and uniformity without significantly complicating the fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The gate seal reduces defects and improves the uniformity of the gate stack, leading to more reliable device performance and increased yield by preventing gate extrusion and enhancing the interface between the gate stack and spacers.
Implementation Method 1
A gate seal is formed around the placeholder gate before depositing the gate spacer, providing a barrier against extrusion
Implementation Method 2
providing a barrier against extrusion and improving surface uniformity, reducing defects and enhancing the adhesion of the gate spacer
Implementation Method 3
enhancing the adhesion of the gate spacer, thereby improving the fabrication process and device reliability
Data Source
AI summary
Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.