Gate Separation Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices become more complex and smaller in size, parasitic capacitance increases, reducing their speed and reliability, which existing technologies have not adequately addressed.
Innovation Solution
The semiconductor device incorporates a separation structure with a first and second conductive pattern stacked sequentially around the channel pattern, and a separation structure disposed between gate structures, optimizing the distance and dielectric material to reduce parasitic capacitance between the gate and source/drain patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the size of transistors and layers is decreased to increase integration, then device complexity and functionality are improved, but parasitic capacitance increases which reduces operation speed and reliability
Solution Approach 1:
The gate structure is segmented into multiple conductive patterns (first conductive pattern and second conductive pattern) stacked sequentially around the channel pattern. This segmentation allows independent optimization of each conductive layer's dimensions and positioning, enabling reduced parasitic capacitance while maintaining device functionality. The separation structure further segments the gate into distinct regions with different electrical characteristics.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional stacked configuration where conductive patterns are arranged in multiple layers around the channel. This dimensional change allows the gate to surround the channel pattern on multiple sides, increasing control efficiency and enabling parasitic capacitance reduction through optimized vertical and lateral spacing between conductive elements.
2Productivity
If conductive layers are placed closer together to reduce device size, then integration density is improved, but parasitic capacitance between conductive layers increases
Solution Approach 1:
A separation structure is introduced as an intermediary element between the first and second conductive patterns. This separation structure, extending in the first direction and positioned between adjacent gate structures, acts as a dielectric barrier that reduces parasitic capacitance coupling between conductive layers while allowing the gate to maintain its wrapping configuration around the channel for high integration density.
Solution Approach 2:
The gate structure employs non-uniform spacing between conductive patterns, with the separation structure creating larger spacing in specific regions where parasitic capacitance is most problematic. This local quality adjustment allows optimized capacitance reduction in critical areas while maintaining tight integration elsewhere in the device structure.
Data Source
AI summary
A semiconductor device may include: a substrate; a lower pattern extending from the substrate in a first direction; a channel pattern disposed on the lower pattern; a source/drain pattern disposed on sides of the channel pattern; a first gate structure and a second gate structure extending in a second direction intersecting the first direction and surrounding respective portions of the channel pattern; and a separation structure disposed between the first gate structure and the second gate structure, and including a first portion extending in the first direction and a second portion protruding from the first portion toward the channel pattern, wherein the first gate structure includes first and second conductive patterns stacked sequentially from the respective portion of the channel pattern, and a length of the second conductive pattern in the second direction is equal to or greater than a length of the second portion in the second direction.