Gate Separation Spacer Structure for Stable Scaled FETs

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Solution Overview

Problem

As semiconductor devices become highly integrated, it is challenging to meet the level of transistor performance required by users, particularly in maintaining operation stability and reliability of transistors due to the decrease in gate and channel lengths of field-effect transistors (FETs).

Innovation Solution

The semiconductor device incorporates a novel structure with first and second active patterns, field insulating films, gate structures, and connecting spacers, including gate separation structures with a gate separation liner and filling film, which enhance the separation and stability of gate structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If gate and channel lengths of FETs are decreased to achieve higher integration, then device density increases, but transistor operation stability and reliability deteriorate

Engineering Contradiction:
Improvedevice integration densityVSAvoidtransistor operation stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The gate structure is segmented into multiple components: gate electrode, gate insulating film, and gate spacer. The gate spacer is further divided into first and second gate spacers positioned at opposite sides. This segmentation allows each component to be independently optimized for its specific function while collectively maintaining transistor reliability at scaled dimensions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate spacer acts as an intermediary structure between the gate electrode and the source/drain regions. It provides mechanical support and electrical isolation, enabling the gate electrode to maintain proper positioning and function even as overall device dimensions are reduced for higher integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If gate structures are closely spaced to increase integration density, then area utilization improves, but gate structure stability and separation deteriorate

Engineering Contradiction:
Improvearea utilizationVSAvoidgate structure separation
Core Design Contradiction:
Area of stationary objectVSStability of the object's composition

Solution Approach 1:

The spacing structure is segmented into multiple gate spacers positioned at opposite sides of the gate electrode. This distributed segmentation provides enhanced structural support and maintains adequate separation between adjacent gate structures, allowing closer spacing while preserving stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Gate spacers are strategically positioned at specific locations (opposite sides) of the gate electrode where structural support is most needed. This localized placement optimizes the use of space while maintaining gate structure separation and stability in critical regions.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12477792B2Method for manufacturing a semiconductor device
Publication Date: 2025.11.18 SAMSUNG ELECTRONICS CO LTD
  • US12477792B2 patent drawing
  • US12477792B2 patent drawing
  • US12477792B2 patent drawing

AI summary

A semiconductor device includes first and second active patterns, a field insulating film between the first and second active patterns, a first gate structure intersecting the first active pattern and including a first gate electrode and a first gate spacer, a second gate structure intersecting the second active pattern and including a second gate electrode and a second gate spacer, a gate separation structure on the field insulating film between the first and second gate structures, the gate separation structure including a gate separation filling film on a gate separation liner, and a connecting spacer between the gate separation structure and the field insulating film, the connecting spacer protruding from a top surface of the field insulating film, and the gate separation liner contacting the connecting spacer and extending along a top surface and sidewalls of the connecting spacer and along the top surface of the field insulating film.