Gate Shift Register Adaptive Voltage Control
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Solution Overview
Problem
Existing gate shift registers in flat panel displays suffer from device degradation over time, leading to unstable scan pulse output due to increased threshold voltage in transistors, which affects the generation of gate high and low voltages, causing degradation of pull-down transistors and resulting in undesired waveform generation.
Innovation Solution
A gate shift register with adaptively adjusted variable high-potential voltage applied to the QB node, sensed and calculated by a threshold voltage sensing circuit and VDD regulator circuit, to compensate for shifts in the threshold voltage of pull-down transistors, thereby stabilizing the output of scan pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a constant high-potential voltage is applied to the QB node, then the pull-down transistor can be turned on effectively during the second output period, but the threshold voltage of the pull-down transistor increases over time due to gate-bias stress, causing device degradation and unstable scan pulse output
Solution Approach 1:
The patent applies a variable high-potential voltage to the QB node instead of a constant voltage. The voltage level is dynamically adjusted based on the threshold voltage of the pull-down transistor, which changes over time due to degradation. This dynamic adjustment compensates for threshold voltage shifts and maintains stable transistor operation throughout the display device's lifespan.
Solution Approach 2:
The patent employs a threshold voltage sensing circuit that continuously monitors the threshold voltage of the pull-down transistor and provides feedback to a VDD regulator circuit. Based on this feedback, the regulator adjusts the high-potential voltage applied to the QB node, creating a closed-loop control system that maintains optimal transistor performance despite degradation.
2Duration of action of stationary object
If the threshold voltage of the pull-down transistor increases due to prolonged exposure to high-potential voltage, then device degradation accelerates, but reducing the voltage may prevent effective turning on of the transistor
Solution Approach 1:
The patent changes the parameter of high-potential voltage from a fixed value to a variable value that adapts to the transistor's degradation state. The voltage level is adjusted according to the measured threshold voltage, ensuring the transistor remains effectively switchable throughout its operational life without accelerating degradation.
3Reliability
If adaptively adjusted variable high-potential voltage is applied to compensate for threshold voltage shifts, then device degradation is minimized and scan pulse output is stabilized, but the device complexity increases due to additional sensing and regulation circuits
Solution Approach 1:
The patent introduces intermediary circuits (threshold voltage sensing circuit and VDD regulator circuit) that mediate between the power supply and the pull-down transistor. These intermediary components enable adaptive voltage adjustment without requiring fundamental changes to the gate shift register architecture, balancing improved reliability with acceptable complexity.
Data Source
AI summary
According to an embodiment, a gate shift register includes a plurality of stages cascade-connected to each other. An nth one of the stages includes: a pull-up transistor that outputs any one of gate shift clocks as an nth scan pulse of a gate high voltage in accordance with the potential of a Q node; a pull-down transistor that is connected to the pull-up transistor through an output node, and outputs a low-potential voltage as an nth scan pulse of a gate low voltage in accordance with the potential of a QB node; and a switching circuit that charges and discharges the Q node and the QB node, respectively, or vice versa in response to a set signal and a reset signal, wherein an adaptively adjusted variable high-potential voltage is applied to the QB node to correspond to a shift in the threshold voltage of the pull-down transistor.