Gate Shift Register with BTS Compensation for Oxide TFT Reliability
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Solution Overview
Problem
The reliability of scan driving circuits in flat panel displays is reduced due to the inability of oxide TFTs to recover from positive bias stress, leading to degradation of threshold voltage and reduced lifespan of the circuit.
Innovation Solution
A gate shift register design that includes a BTS compensation unit to periodically discharge the QB node, reducing gate bias stress by alternating the potential of the QB node, thereby extending the lifespan of the scan driving circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If oxide TFTs are used in scan driving circuits, then electron mobility is improved (20 to 30 times higher than a-Si:H TFT), but the TFTs cannot recover from positive bias stress, leading to threshold voltage degradation and reduced reliability
Solution Approach 1:
The patent applies periodic action by alternately driving two pull-down TFTs (Tpd1 and Tpd2) connected to QB1 and QB2 nodes respectively. This periodic switching allows each TFT to experience intervals of positive bias stress followed by recovery periods, preventing cumulative threshold voltage degradation while maintaining the high electron mobility advantage of oxide TFTs
Solution Approach 2:
The patent implements discarding and recovering by having one pull-down TFT active while the other is in recovery mode. The active TFT handles the driving function while the inactive TFT recovers from bias stress, and they alternate roles periodically. This ensures continuous circuit operation while allowing regular recovery from stress-induced threshold voltage shifts
2Ease of operation
If the QB node is maintained at high potential level for most of one frame period, then the pull-down TFT can function properly, but positive bias stress accumulates in gate electrodes, degrading the TFT performance over time
Solution Approach 1:
The patent uses periodic action by switching between two pull-down TFTs connected to QB1 and QB2 nodes. Each TFT is activated for a portion of the frame period and then deactivated for recovery, creating a periodic on-off pattern that maintains switching functionality while preventing continuous stress accumulation in any single TFT
Solution Approach 2:
The patent applies dynamics by making the pull-down TFT configuration changeable over time through periodic switching. Instead of a static configuration where one TFT bears continuous stress, the system dynamically alternates between two TFTs, allowing the stress distribution to change periodically and enabling recovery periods for each device
Data Source
AI summary
Provided is a gate shift register including a plurality of stages receiving a plurality of clocks to generate gate output signals, in which an n-th stage of the stages dependently connected to each other includes an output node outputting an n-th gate output signal, a pull-up TFT switching a current flow between an input terminal of a clock having an n-th phase and the output node according to a potential of a Q node, a pull-down TFT switching the current flow between an input terminal of a low potential voltage and the output node according to a potential of a QB node, appnd a BTS compensation unit periodically discharging the QB node at a low potential level just after the n-th stage is reset and just until the n-th stage is set in a next frame.