Gate Shift Register Initialization for Parasitic Capacitance Reset
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Solution Overview
Problem
In large-area, high-resolution flat panel displays, parasitic capacitance often prevents proper reset of Q node and QB node potentials, leading to simultaneous activation of pull-up TFTs and multiple scan pulse outputs, degrading display quality and potentially causing over-current issues.
Innovation Solution
A display device with a gate shift register that includes a level shifter to convert a start pulse and N-phase shift clocks into predetermined voltages, with an initialization pulse and sub-initialization period to stabilize node potentials, ensuring proper reset of stages before the driving period, using a reset switch circuit to manage node potentials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the display device is intermittently driven at long time intervals, then power consumption is reduced, but the potentials of Q node and QB node are not reset properly due to parasitic capacitance
Solution Approach 1:
The patent applies preliminary action by implementing an initialization period before the driving period during which initialization pulses are applied to reset the Q node and QB node potentials. This preliminary reset action ensures that when the display device resumes operation after intermittent driving, the nodes are properly initialized despite parasitic capacitance effects, preventing multiple scan pulse outputs while maintaining power savings during idle periods.
2Device complexity
If the potentials of Q node and QB node are not reset properly, then the circuit operation is simplified, but multiple pull-up TFTs are simultaneously turned on causing multiple scan pulse outputs
Solution Approach 1:
The patent implements preliminary action by applying initialization pulses during an initialization period before the driving period to reset node potentials in advance, preventing the harmful effect of simultaneous pull-up TFT activation. Alternatively, the patent applies preliminary anti-action by using reset switch circuits that actively force the Q node to turn-off level and QB node to turn-on level, counteracting the parasitic capacitance effects before they can cause multiple scan pulse outputs.
Solution Approach 2:
The patent introduces intermediary elements including reset switch circuits with reset transistors that act as mediators to force proper node potentials, and initialization pulses that serve as intermediary signals to reset the circuit state. These intermediaries ensure proper sequencing of pull-up TFT activation without adding significant complexity to the overall circuit operation.
3Speed
If multiple pull-up TFTs are simultaneously turned on, then the initialization process is faster, but over-current occurs and module power supply is paralyzed
Solution Approach 1:
The patent applies preliminary action by resetting the Q node and QB node potentials during an initialization period before the driving period begins. This advance reset prevents simultaneous activation of multiple pull-up TFTs during operation, thereby avoiding over-current conditions and module power supply paralysis while maintaining fast initialization through efficient pulse sequencing.
Solution Approach 2:
The patent implements preliminary anti-action by using reset switch circuits that actively prevent simultaneous turn-on of multiple pull-up TFTs. The reset transistors force the Q node to turn-off level and QB node to turn-on level, counteracting the tendency toward simultaneous activation before it can occur, thus preventing over-current effects while allowing fast initialization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the initial operation of the gate shift register, preventing multiple scan pulse outputs and over-current issues, thereby enhancing display quality and reliability.
Implementation Method 1
a level shifter shifting a start pulse, an initialization pulse, and N-phase shift clocks, N is an integer equal to or greater than 2, to a predetermined voltage
Implementation Method 2
the Q node potential of each stage, initialized to the turn-off level, must be set to the turn-on level prior to the timing of scan pulse output and reset to the turn-off level in synchronization with the timing of completion of scan pulse output
Data Source
AI summary
Disclosed is a display device that comprises: a display panel; a level shifter shifting a start pulse, an initialization pulse, and N (N is an integer equal to or greater than 2)-phase shift clocks to a predetermined voltage; and a gate shift register comprising multiple stages respectively connected to scan lines of the display panel and shifting the start pulse in response to the N-phase shift clocks within a driving period defined by the start pulse to sequentially output a scan pulse, wherein the stages are simultaneously reset in response to the initialization pulse and the N-phase shift clocks within an initialization period preceding the driving period.