Gate Shift Register Shared Carry Clock Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing organic light emitting display apparatus faces challenges in achieving a narrow bezel design due to the large number of clock lines required, which increases parasitic capacitance and distorts shift clocks, degrading image quality.
Innovation Solution
A gate shift register design with shared carry clock lines, where the number of shared carry clock lines is half the number of scan clock lines, and each stage pair shares a carry shift clock, reducing the overall number of clock lines and minimizing coupling effects between clock lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of clock lines is increased to provide separate carry shift clocks for each stage, then the shift clock generation capability is improved, but the parasitic capacitance increases and the bezel region cannot be reduced
Solution Approach 1:
The patent merges the carry shift clock lines by making adjacent stages share the same carry shift clock line. Specifically, odd-numbered stages (1st, 3rd, 5th, etc.) share one carry shift clock line, and even-numbered stages (2nd, 4th, 6th, etc.) share another carry shift clock line. This merging approach reduces the total number of clock lines while maintaining the necessary shift clock generation capability across all stages.
Solution Approach 2:
The patent implements multi-functionality by designing carry shift clock lines that serve multiple stages simultaneously. A single carry shift clock line functions as the carry clock source for multiple adjacent stages, allowing the same physical line to perform the clocking function for several stages rather than requiring dedicated lines for each stage.
2Length of moving object
If clock lines are placed close to each other to reduce bezel width, then the bezel region is reduced, but the coupling effect distorts the shift clocks and degrades image quality
Solution Approach 1:
By merging carry shift clock lines so that adjacent stages share the same line, the patent reduces the total number of clock lines. This reduction allows clock lines to be spaced farther apart, thereby reducing the parasitic capacitance and coupling effects between adjacent lines while still achieving a compact bezel region.
3Object-affected harmful factors
If the number of clock lines is reduced to minimize parasitic capacitance, then the coupling effect is reduced, but the capability to generate different phase shift clocks is compromised
Solution Approach 1:
The patent segments the stages into two groups: odd-numbered stages and even-numbered stages. Each group shares a common carry shift clock line, creating distinct clocking domains. This segmentation allows the system to maintain different phase relationships between clock lines while using fewer total lines, as each segmented group can be clocked independently with appropriate phase shifts.
Solution Approach 2:
The patent introduces a new dimension to the clocking scheme by using selective clock line connections. Different stages are connected to different carry shift clock lines based on their stage number (odd or even), creating a multi-dimensional clock distribution network that maintains phase diversity despite having fewer physical clock lines.
Data Source
AI summary
Provided is a gate shift register having multiple stages including a plurality of scan clock lines supplying scan shift clocks having different phases required for generating a scan control signal to the stages, and a plurality of shared carry clock lines supplying carry shift clocks having different phases required for generating a carry signal to the stages, wherein the number of the shared carry clock lines is half of the number of the scan clock lines and each of stage pairs including an odd-numbered stage and an even-numbered stage adjacent to each other share one carry shift clock.