Gate Sidewall Selective Removal for FinFET Spacer Protection
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Solution Overview
Problem
Conventional gate-last processing in semiconductor device fabrication is susceptible to silicon nodule defect formation during epitaxial growth, particularly in FINFETs, due to sacrificial gate material issues, which becomes more critical as device dimensions shrink.
Innovation Solution
The method involves providing a gate structure with doped regions along the sidewalls, selectively removing these regions to partially undercut the protective layers, and forming sidewall spacers that fill the undercut areas, thereby enhancing spacer protection and isolation to prevent nodule defect formation during subsequent epitaxial processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate-last processing is used with sacrificial gate material, then the gate structure can be formed and replaced with metal gate, but silicon nodule defects form during epitaxial growth
Solution Approach 1:
The patent applies preliminary action by performing selective removal of gate structure sidewall portions before the epitaxial growth process. This preemptive modification of the gate structure eliminates the conditions that would otherwise cause silicon nodule defects during subsequent epitaxial growth, thereby preventing defects before they occur.
Solution Approach 2:
The patent extracts or removes the problematic gate structure sidewall portions that cause silicon nodule defect formation. By selectively removing these specific portions of the gate structure sidewalls, the source of the harmful effect is eliminated while preserving the functional gate structure.
2Reliability
If sidewall spacers are formed to protect gate structures, then gate isolation is improved, but severe spacer pull-down occurs
Solution Approach 1:
The patent applies local quality by selectively removing portions of the gate structure sidewalls at specific locations rather than uniformly modifying the entire gate structure. This localized modification allows sidewall spacers to be properly formed and adhered to specific regions, improving gate isolation while preventing severe spacer pull-down in critical areas.
Data Source
AI summary
Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.