Gate Signal Drive Circuit Reducing Power via Segmented Transistors
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Solution Overview
Problem
Existing gate signal line drive circuits in liquid crystal display devices face challenges in reducing power consumption due to parasitic capacitance and blunted signal waveforms, which affect the quality of the display by increasing power consumption and degrading brightness.
Innovation Solution
A gate signal line drive circuit is designed with a combination of high and low voltage application switching elements and control elements, utilizing multi-phase clock signals to manage the switching of gate signals, reducing the element size of transistors and minimizing parasitic capacitance, thereby reducing power consumption and improving signal waveform steepness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the element size of transistor T5 is reduced to decrease parasitic capacitance, then power consumption is reduced, but the signal waveform becomes blunted and display quality degrades
Solution Approach 1:
The patent divides the single transistor T5 into multiple transistors (T5A, T5B, T5C) that operate in sequence during different phases of the clock cycle. This segmentation allows each transistor to be smaller with less parasitic capacitance, while collectively they maintain the required drive capability and signal waveform quality.
Solution Approach 2:
The patent employs multi-phase clock signals (Vn, Vn+2, Vn+4) that operate in periodic phases to control the sequential operation of transistors T5A, T5B, and T5C. Each transistor is activated during its specific phase, distributing the switching action over time and reducing the parasitic capacitance burden on any single transistor while maintaining continuous drive capability.
2Manufacturing precision
If transistor T5 is kept in on state during signal low period to maintain gate signal line voltage, then display quality is maintained, but power consumption increases due to continuous charge and discharge current
Solution Approach 1:
The patent uses multi-phase clock signals to periodically activate different transistors (T5A, T5B, T5C) in sequence. During the signal low period, the clock signals continue to cycle through phases, causing the transistors to switch on and off in a periodic manner while maintaining the overall voltage level on the gate signal line. This periodic switching reduces continuous charge-discharge current and power consumption.
Solution Approach 2:
The patent ensures continuous voltage maintenance on the gate signal line by having multiple transistors overlap in their operation. While individual transistors switch off during phase transitions, the sequential activation of T5A, T5B, and T5C ensures that voltage control is continuously maintained without interruption, preserving display quality while reducing power consumption through phased operation.
Data Source
AI summary
A gate signal line drive circuit whose power consumption is reduced, is provided. In the gate signal line drive circuit having plural basic circuits outputting respective gate signals, each basic circuit includes a high voltage application switching element to which a first basic clock signal having high voltage in a signal high period is input, a low voltage application switching element that turns on at timing starting a signal low period, and outputs a low voltage, and a first low voltage application on control element having an input terminal to which a second basic clock signal subsequent to the first basic clock signal is input, and which turns on according to the signal high period, and outputs the voltage of the second basic clock signal to the control terminal of the low voltage application switching element.