Gate Signal Masking Circuit for Low-Power Independent Waveform Control

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Solution Overview

Problem

Existing display technologies face challenges in reducing power consumption when displaying static images or operating in always-on modes, as the driving frequency of the display panel cannot be adequately decreased due to the reliance on carry signals, and the waveforms of data initialization and compensation gate signals cannot be generated differently.

Innovation Solution

A gate signal masking circuit is introduced, which includes switching elements and capacitors to control the output of gate signals based on carry and enable signals, allowing for multiple divisions of driving frequency and distinct waveform generation for data initialization and compensation gate signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the driving frequency of the display panel is decreased to reduce power consumption, then power consumption is reduced, but the gate signal output cannot be properly controlled due to carry signal dependency

Engineering Contradiction:
Improvepower consumptionVSAvoidgate signal control flexibility
Core Design Contradiction:
Use of energy by moving objectVSEase of operation

Solution Approach 1:

The gate signal generation circuit is divided into multiple independent gate signal generators, each capable of generating gate signals independently without relying on carry signals from previous stages. This segmentation allows each generator to operate autonomously at different frequencies, enabling frequency division for power consumption reduction while maintaining control flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate signal generators are designed with dynamic operation capabilities, allowing them to adjust their operating frequencies based on display content requirements. The circuit includes control nodes and switching elements that enable flexible adjustment of gate signal timing and frequency, transforming a static carry-dependent system into a dynamic independent control system.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If a single gate signal generator is used for both data initialization and compensation gate signals, then device complexity is reduced, but the waveforms cannot be generated differently

Engineering Contradiction:
Improvegate signal generator structureVSAvoidwaveform generation capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The gate signal generation function is segmented into separate dedicated generators: a first gate signal generator for data initialization gate signals and a second gate signal generator for compensation gate signals. Each generator is independently designed to produce its specific waveform type, eliminating the limitation of a single shared generator while maintaining manageable system complexity through modular architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each gate signal generator is optimized with specific local characteristics suited to its particular function. The first generator incorporates circuit configurations optimized for data initialization waveform requirements, while the second generator is configured for compensation gate signal requirements, allowing each to deliver optimal performance for its specific purpose.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12548496B2Gate signal masking circuit, gate driver including the same and display apparatus including the same
Publication Date: 2026.02.10 SAMSUNG DISPLAY CO LTD
  • US12548496B2 patent drawing
  • US12548496B2 patent drawing
  • US12548496B2 patent drawing

AI summary

A gate signal masking circuit includes: a connection transistor connecting a first control node and a first transistor based on a connection signal; the first transistor connected to a masking node, the connection transistor and a second control node; a second transistor including a control electrode receiving a carry signal, a first electrode receiving a masking signal and a second electrode connected to a first node; a third transistor including a control electrode receiving an enable signal, a first electrode connected to the first node and a second electrode connected to the masking node; a fourth transistor including a control electrode receiving a second enable signal, a first electrode connected to the masking node and a second electrode connected to a second node; a fifth transistor including a control electrode receiving the carry signal, a first electrode connected to the second node and a second electrode receiving a power voltage.