Gate Signal Timing Compensation for Large Display Panels

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Solution Overview

Problem

Large liquid crystal display panels experience RC time delay issues, leading to decreased display quality due to increased resistance-capacitance time delays, particularly affecting areas farthest from the gate driving part, resulting in low luminance, color mixing, and ghosting effects.

Innovation Solution

A method of driving the display panel involves generating a reference gate signal delayed by a predetermined period from a gate signal applied to an area with minimal RC delay and comparing it with an input gate signal from an area with maximum RC delay, selectively controlling the delay time of each gate signal to synchronize or delay the rising time of the gate signal based on the comparison, using a display apparatus with a data driver circuit, gate driver circuit, reference signal generator, delay determiner, control signal generator, and timing controller.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the display panel size is increased to provide a larger display area, then the display area is improved, but the RC time delay increases causing degraded display quality

Engineering Contradiction:
Improvedisplay areaVSAvoiddisplay quality
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by differentiating the gate signal delay time based on the spatial position of gate lines within the display panel. Specifically, gate lines in different regions (first end area vs. second area) are assigned different delay characteristics to compensate for their respective RC time delays. This localized adjustment ensures that each region receives appropriately timed gate signals, maintaining uniform display quality across the entire large-sized panel.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If the display panel size is increased, then the display area is improved, but the RC time delay causes charging time extension leading to low luminance

Engineering Contradiction:
Improvedisplay areaVSAvoidluminance
Core Design Contradiction:
Area of stationary objectVSIllumination intensity

Solution Approach 1:

The patent changes the temporal parameter (delay time) of gate signals based on their spatial position within the display panel. By adjusting the delay time parameter for gate lines in different areas, the system compensates for RC time delays and ensures that data signals are properly charged into pixels within the required time frame, thereby maintaining adequate luminance across the entire large display area.

Inventive Principle:
Principle #35Parameter changes

3Area of stationary object

If the display panel size is increased, then the display area is improved, but the RC time delay causes charging ratio decrease resulting in display quality degradation

Engineering Contradiction:
Improvedisplay areaVSAvoidcharging ratio
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent implements local quality by applying region-specific delay times to gate signals. Gate lines in the first end area receive different delay treatment compared to those in the second area, where RC time delay is maximum. This localized compensation ensures that each region achieves its required charging ratio, maintaining reliable display performance across the entire large panel.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9865217B2Method of driving display panel and display apparatus
Publication Date: 2018.01.09 SAMSUNG DISPLAY CO LTD
  • US9865217B2 patent drawing
  • US9865217B2 patent drawing
  • US9865217B2 patent drawing

AI summary

A method of driving a display panel includes generating a reference gate signal delayed by a predetermined period from a gate signal applied to a gate line disposed in a first end area of the display panel, the first end area being an area in which a RC delay of a data line is the smallest, receiving an input gate signal applied to a gate line disposed in a second area of the display panel, the second area being an area in which the RC delay of the data line is the largest; and selectively controlling a delay time of each of the plurality of gate signals applied to each of the plurality of gate lines according to a result of comparison between the reference gate signal and the input gate signal.