Gate Structure Oxidation Protection Using Silane Sealing Layer
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Solution Overview
Problem
The use of high-Fermi energy materials in memory devices, such as flash NAND and phase change memories, poses a risk of corruption due to their reactivity with atmospheric elements and oxidation, affecting the electrical properties of transistors during the fabrication process.
Innovation Solution
A process flow involving multiple etches and the deposition of an isolating layer is employed to form a gate stack, where spacers provide protection from oxidation, ensuring the integrity of high-Fermi energy materials like TaN and tungsten in the gate structure, thereby preventing stress and maintaining electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-Fermi energy materials are used in memory devices to enable scaling and satisfactory performance, then device performance and scalability are improved, but the materials become reactive to atmospheric elements and oxidation, corrupting electrical properties
Solution Approach 1:
A silane-based sealing layer is deposited as an intermediary between the high-Fermi energy material (control gate) and the atmosphere. This sealing layer acts as a mediator that prevents direct contact between the reactive material and oxidizing environmental elements, thereby protecting the electrical properties while allowing the high-Fermi energy material to function
Solution Approach 2:
The patent creates an inert protective environment by depositing a silane-based sealing layer that forms a barrier against atmospheric elements. This effectively creates a localized inert atmosphere around the high-Fermi energy material, preventing oxidation and chemical reactions that would otherwise corrupt the electrical properties
2Device complexity
If a single etch process is used to form the gate stack, then manufacturing complexity is reduced, but the high-Fermi energy material walls remain exposed to atmosphere, increasing oxidation risk
Solution Approach 1:
The silane-based sealing layer is deposited preliminarily after the single etch process forms the gate stack. This preliminary action of sealing protects the freshly formed high-Fermi energy material walls before they are exposed to subsequent processing steps or atmosphere, preventing oxidation while maintaining process simplicity
Solution Approach 2:
The sealing layer serves as an intermediary protective barrier that is introduced into the process flow. It mediates between the simple single-etch manufacturing approach and the need for material protection, allowing both simplicity and reliability to coexist
3Productivity
If no protective layer is deposited, then manufacturing steps are minimized, but stress is induced at gate walls and substrate, adversely affecting transistor performance
Solution Approach 1:
The silane-based sealing layer acts as a stress-buffering intermediary between the gate structure and the substrate. It provides a compliant interface that reduces stress concentration at critical interfaces, preventing performance degradation while adding minimal process steps
Solution Approach 2:
The sealing layer is implemented as a thin film that provides protective coverage. This thin film structure offers stress relief and protection without adding significant thickness or complexity to the gate stack, maintaining manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively protects high-Fermi energy materials from oxidation, ensuring the reliability and performance of memory devices by preventing corruption of electrical properties and reducing stress on the gate walls and substrate.
Implementation Method 1
materials having relatively high Fermi energy levels... may be particularly reactive to atmospheric elements and/or flow process by-products. Such a relatively high sensitivity to oxidation may result in such materials having an increased reactivity to oxidizing chemicals
Implementation Method 2
a process flow may include a single etch to selectively etch the conducting material layer, the control gate layer, and to expose the gate oxide layer
Data Source
AI summary
Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device.