Selective Gate Silicidation via Oxide Segmentation
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Solution Overview
Problem
The existing methods for fabricating integrated circuits face challenges in selectively silicidating gate electrodes without simultaneously silicidating the adjacent semiconductor substrate, requiring complex mask patterning and complicating the process.
Innovation Solution
A method involving the formation of an oxide layer on the gate electrodes and semiconductor substrate, followed by a cover layer, back etching to expose portions of the oxide layer, and subsequent removal to allow for silicidation of the gate electrodes while maintaining a portion of the oxide layer between them, preventing silicidation of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicidation methods are used, then gate electrode conductivity is improved, but the semiconductor substrate also undergoes unwanted silicidation
Solution Approach 1:
The substrate surface is segmented into different regions with different oxide layer thicknesses: thicker oxide regions between gate electrodes that prevent silicidation, and thinner oxide regions on gate electrodes that allow silicidation. This spatial segmentation enables selective silicidation of only the desired areas.
Solution Approach 2:
Different regions of the substrate are given different local properties through selective oxide removal. The gate electrode regions have thin oxide allowing metal diffusion and silicidation, while the inter-gate regions have thick oxide preventing metal diffusion and silicidation, creating locally differentiated quality.
2Manufacturing precision
If mask patterning is used to prevent substrate silicidation, then selective silicidation is achieved, but process complexity increases
Solution Approach 1:
The oxide layer thickness is differentiated in advance before the silicidation process. By pre-forming thicker oxide in inter-gate regions and thinner oxide on gate electrodes, the substrate is prepared beforehand to naturally guide selective metal diffusion and silicidation without requiring complex mask patterning during the silicidation step.
Solution Approach 2:
The oxide layer serves as an intermediary barrier that controls metal diffusion. By varying oxide thickness, it mediates between the metal layer and substrate, allowing diffusion only where the oxide is thin (gate electrodes) while blocking diffusion where oxide is thick (inter-gate regions), thereby simplifying the overall process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables selective silicidation of gate electrodes without forming metal silicide in the semiconductor substrate, simplifying the processing and maintaining well-defined electronic characteristics, thus avoiding significant threshold variations.
Implementation Method 1
maintaining a portion of the oxide layer between the gate electrodes, preventing silicidation of the substrate
Implementation Method 2
performing silicidation of the exposed upper portions of the gate electrodes
Data Source
AI summary
A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.