Gate Oxide and Silicide Layout for Lateral Diffusion Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in improving transistor operation performance and manufacturing yield due to the influence of thicker gate oxide layers, particularly in high voltage environments, where lateral diffusion of nickel silicide layers affects device performance.
Innovation Solution
Control the ratio of nitrogen trifluoride (NF3) to ammonia (NH3) in the SiCoNi process to suppress lateral diffusion of the nickel silicide layer, ensuring a specific distance between the nickel silicide layer and the gate structure, thereby enhancing the semiconductor device's operation performance and manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a thicker gate oxide layer is used to enable high voltage processing, then the operation voltage capability is improved, but the lateral diffusion of nickel silicide layer increases which deteriorates device performance
Solution Approach 1:
The patent changes the chemical parameters of the SiCoNi process by controlling the ratio of nitrogen trifluoride (NF3) to ammonia (NH3) within 0.35-0.45, which modifies the etching chemistry to suppress lateral diffusion of nickel silicide while enabling thicker gate oxide layers for high voltage operation
Solution Approach 2:
The patent introduces a fluorinated silicon oxide layer as an intermediary between the gate oxide and nickel silicide layer. This intermediate layer, formed through the controlled SiCoNi process, acts as a diffusion barrier that prevents nickel from laterally spreading while allowing vertical gate oxide thickening for high voltage capability
2Adaptability or versatility
If the gate oxide layer thickness is increased to modify transistor operation voltage, then the voltage processing capability is improved, but the manufacturing conditions of other parts are influenced which deteriorates overall device performance
Solution Approach 1:
The patent modifies the SiCoNi process parameters (NF3:NH3 ratio of 0.35-0.45) to create a fluorinated silicon oxide layer that enables thicker gate oxide formation without adversely affecting other manufacturing steps, thus improving voltage processing capability while maintaining manufacturing compatibility
Solution Approach 2:
The patent performs the SiCoNi process with controlled gas ratios before final gate oxide thickening, preliminarily forming a fluorinated interface layer that prepares the structure for subsequent high voltage gate oxide formation without compromising other manufacturing conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The controlled ratio of NF3 to NH3 in the SiCoNi process effectively reduces off-current and improves the overall performance of semiconductor devices by managing nickel silicide layer diffusion, leading to enhanced manufacturing yield and operational efficiency.
Implementation Method 1
a range of a ratio of nitrogen trifluoride (NF3) to ammonia (NH3) used in a SiCoNi process is controlled for suppressing lateral diffusion of a nickel silicide layer formed subsequently
Data Source
AI summary
A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate is provided, and a gate oxide layer, a gate structure, and a spacer structure are formed on the semiconductor substrate. The gate oxide layer is located between the gate structure and the semiconductor substrate in a vertical direction, and the spacer structure is located on a sidewall of the gate structure. A SiCoNi process is performed, and a ratio of nitrogen trifluoride (NF3) to ammonia (NH3) used in the SiCoNi process is greater than or equal to 0.35 and less than or equal to 0.4. A nickel silicide layer is formed in the semiconductor substrate after the SiCoNi process, and a part of the nickel silicide layer is located under the spacer structure in the vertical direction.