Gate-Sinking pHEMTs with Composite Schottky Layer
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Solution Overview
Problem
Conventional monolithic integrated circuit devices with gate-sinking pHEMTs face challenges in achieving uniform pinch-off voltages across a wafer and from wafer to wafer, requiring complex fabrication processes and leading to variability in transistor performance due to variations in gate electrode thickness and thermal treatment conditions.
Innovation Solution
A composite Schottky layer structure with stacked semiconductor layers is implemented, allowing precise control of the gate metal sinking depth to reduce pinch-off voltage variation and enable tuning of pHEMTs to desired positive or negative values, using a multi-layer structure with a semiconductor substrate, epitaxial layers, and specific Schottky layer configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-sinking technique is used to achieve E-mode pHEMTs, then positive pinch-off voltage is obtained, but uniformity of pinch-off voltage across wafer and from wafer to wafer deteriorates due to variations in gate electrode thickness and thermal treatment conditions
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional metals to phase-change material (GST), which allows the gate electrode thickness to be dynamically adjusted through phase transitions. This enables precise control of the gate-to-channel distance and pinch-off voltage without requiring extremely tight control of deposition thickness, thereby improving pinch-off voltage uniformity across wafers.
Solution Approach 2:
The patent utilizes the phase transition property of GST material between crystalline and amorphous states to control the gate electrode characteristics. By controlling the phase state, the effective gate thickness can be precisely adjusted, enabling uniform pinch-off voltage control across different wafers and reducing variability in transistor performance.
2Reliability
If gate-sinking technique is used to achieve E-mode pHEMTs, then positive pinch-off voltage is obtained, but uniformity of pinch-off voltage from wafer to wafer deteriorates due to variations in thermal treatment conditions
Solution Approach 1:
The patent changes the gate electrode material to phase-change material, which allows thickness control through phase transitions rather than relying solely on thermal treatment. This reduces sensitivity to thermal treatment condition variations, improving wafer-to-wafer uniformity of pinch-off voltage.
Solution Approach 2:
The patent performs preliminary phase transition treatment to establish the desired gate electrode characteristics before final device operation. By pre-configuring the gate thickness through phase transitions, the device becomes less sensitive to subsequent thermal variations during operation and fabrication.
3Manufacturing precision
If conventional gate electrode materials are used, then fabrication process is simpler, but pinch-off voltage control precision deteriorates
Solution Approach 1:
The patent employs phase transition of GST material to achieve precise pinch-off voltage control. The phase transition mechanism allows for dynamic adjustment of gate thickness, providing superior voltage control precision compared to conventional materials, despite the added complexity of phase transition processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces pinch-off voltage variation across wafers and from wafer to wafer, simplifies the fabrication process, and allows for precise tuning of pHEMTs, improving transistor uniformity and performance while reducing defects and surface states.
Implementation Method 1
the first deposited gate metal diffuses uniformly, consistently, and fully into the Schottky barrier layer
Data Source
AI summary
A monolithic integrated circuit device formed in a multi-layer structure comprises a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT. A Schottky layer in the multi-layer structure contains at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween. The gate-sinking pHEMTs each includes a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary. The first gate metal layers are in contact with the topmost stacked region of the Schottky layer. The gate-sinking regions are beneath the first gate metal layers. The gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT, which is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT, locates within 10 Å above or below one of the stacked region contact interfaces of the Schottky layer.