Gate-Sinking pHEMTs With Graded Schottky Barrier for Voltage Uniformity
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Solution Overview
Problem
Conventional gate-sinking pHEMTs face challenges in achieving uniform pinch-off voltage across and between wafers due to variations in gate metal thickness, thermal treatment temperature, and duration, resulting in high standard deviation of transistor performance.
Innovation Solution
The design incorporates a Schottky layer with stacked regions of semiconductor materials, where the gate metal layer is deposited within a gate recess defined by one of the stacked regions, allowing precise control of the gate-to-channel distance, thereby ensuring uniformity of the pinch-off voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-sinking technique is used to achieve E-mode pHEMTs, then positive pinch-off voltage is obtained, but high variability in pinch-off voltage across wafer occurs
Solution Approach 1:
The patent changes the material composition parameter of the Schottky barrier layer by introducing a graded structure with varying Al composition (x value) from 0.3 to 0.7. This gradual parameter change enables controlled metal diffusion depth while maintaining uniform pinch-off voltage across the wafer, resolving the contradiction between achieving positive threshold voltage and controlling voltage uniformity.
Solution Approach 2:
The patent applies local quality by creating a non-uniform Schottky barrier layer where different regions have different Al composition gradients. The graded structure allows the gate metal to diffuse to different depths in different regions, enabling precise control of the gate-to-channel distance and achieving uniform pinch-off voltage across the entire wafer despite variations in processing conditions.
2Ease of manufacture
If variations in gate metal layer thickness, thermal treatment temperature, and duration occur, then manufacturing process flexibility is maintained, but bottom boundary control of gate-sinking region becomes difficult
Solution Approach 1:
The graded Al composition structure (x=0.3 to x=0.7) acts as a parameter gradient that controls the diffusion process. Even when thermal treatment parameters vary, the gradient ensures that the gate metal diffuses to a consistent effective depth, maintaining precise boundary control while allowing flexibility in processing parameters.
Solution Approach 2:
The graded Schottky barrier layer acts as an intermediary structure between the gate metal and the channel layer. This intermediate graded region buffers the effects of variations in gate metal thickness and thermal treatment parameters, ensuring that the final gate-sinking depth and pinch-off voltage remain uniform across the wafer.
3Reliability
If conventional gate-sinking structure is used, then E-mode operation is achieved, but standard deviation of pinch-off voltage remains high
Solution Approach 1:
The patent uses a composite Schottky barrier layer structure combining multiple materials with different Al compositions (AlGaAs layers with x=0.3, 0.4, 0.5, 0.6, 0.7). This composite graded structure enables precise control of gate metal diffusion while maintaining E-mode operation, achieving both reliable enhancement-mode operation and low standard deviation in pinch-off voltage.
Solution Approach 2:
By continuously varying the Al composition parameter (x value) through the Schottky barrier layer thickness, the patent creates a parameter gradient that controls the electrical properties. This parameter change approach ensures uniform pinch-off voltage across the wafer while maintaining the required E-mode operation characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the standard deviation of pinch-off voltage across wafers, enhancing device performance and quality, and improving economic benefits through improved uniformity and reliability.
Implementation Method 1
the first gate metal layer 950 of the gate electrode 95 is formed on the Schottky barrier layer 94... Under proper thermal treatment, a gate-sinking region 99 is observed beneath the first gate metal layer 950 of the gate electrode 95 within the Schottky barrier layer 94
Data Source
AI summary
A gate-sinking pseudomorphic high electron mobility transistor comprises a compound semiconductor substrate overlaid with an epitaxial structure which includes sequentially a buffer layer, a channel layer, a Schottky layer, and a first cap layer. The Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material. Each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween. In any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material. A gate-sinking region is beneath the first gate metal layer of the gate electrode, and the bottom boundary of the gate-sinking region is located at the one of the at least one stacked region contact interface of the Schottky layer.