Gate Size Discretization for Numerical Circuit Synthesis
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Solution Overview
Problem
Existing circuit synthesis approaches are computationally expensive and produce poor quality results due to the iterative trial-and-error method, especially when dealing with large circuit designs and multiple timing constraints across process corners and modes.
Innovation Solution
The proposed solution involves optimizing gate sizes by identifying library cells with optimal input capacitance values, using numerical solvers to compute delays, and iterating through sorted library cells to find cells that improve delay or minimize area without violating timing constraints, employing specific and generic numerical delay models for accurate discretization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error based circuit synthesis approaches are used to optimize gate sizes, then timing constraints can be checked across process corners and modes, but the computational time becomes excessively long and the quality of results deteriorates for large circuit designs
Solution Approach 1:
The patent transforms the continuous gate sizing problem into a discrete optimization problem by representing gate sizes as integer multiples of a reference size. This parameter discretization allows the use of efficient combinatorial optimization algorithms instead of iterative trial-and-error methods, significantly reducing computational time while maintaining timing constraint satisfaction across process corners and modes.
Solution Approach 2:
The patent segments the gate sizing optimization into two phases: first solving for continuous optimal sizes using numerical methods, then discretizing these sizes to integer multiples of a reference gate size. This segmentation allows the complex continuous optimization to be decomposed into a simpler discrete selection problem, reducing overall computational burden.
2Reliability
If iterative trial-and-error based circuit synthesis approaches are used to optimize gate sizes, then timing constraints can be verified, but the quality of synthesis results becomes poor for large circuit designs
Solution Approach 1:
By changing the parameter representation from continuous to discrete (integer multiples of reference size), the patent enables exact optimization rather than approximate iterative solutions. This discrete formulation allows finding globally optimal solutions that satisfy timing constraints with higher precision, improving synthesis result quality for large circuit designs.
3Measurement precision
If modern technology libraries with many gate sizes are used, then more accurate timing analysis can be performed, but the computational complexity and optimization time increase significantly
Solution Approach 1:
The patent reduces the complexity of selecting from many library gate sizes by transforming the selection into a discrete mathematical problem where optimal sizes are integer multiples of a reference size. This parameter transformation converts a complex search through many library options into a simpler integer optimization problem, maintaining timing analysis accuracy while reducing optimization complexity.
Data Source
AI summary
Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell, wherein the input capacitance value is determined by a numerical solver that is optimizing the circuit design. Note that the circuit design may be optimized for different objective functions, e.g., best delay, minimal area under delay constraints, etc. Next, the embodiments can identify an initial library cell in a technology library whose input capacitance value is closest to the optimal input capacitance value. The embodiments can then use the initial library cell to attempt to identify a better (in terms of the objective function that is being optimized) library cell in the technology library. The delay computations used during this process are also minimized.