Gate Size Optimization via Numerical Delay Models
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Solution Overview
Problem
Existing circuit synthesis approaches, especially those using iterative trial-and-error methods, are inefficient and produce poor results for large circuit designs due to inaccurate delay modeling and the need to check timing constraints across multiple process corners and modes.
Innovation Solution
The use of numerical delay models and a reverse-levelized processing order to optimize gate sizes in a circuit design, where closed-form expressions determine optimal gate sizes based on logical effort, input capacitance, wire resistance, and other circuit parameters, with the option to use these sizes directly or as seed values for further optimization by a numerical solver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error based circuit synthesis approaches are used to optimize gate sizes, then timing constraints can be checked across multiple process corners and modes, but the optimization process takes too long to complete and produces poor quality results for large circuit designs
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing delay characteristics of cells at multiple process corners and modes in lookup tables before the synthesis process. During optimization, these pre-computed delay models enable rapid timing evaluation without requiring full timing analysis, thus maintaining reliability across process variations while dramatically improving optimization speed.
Solution Approach 2:
The patent changes parameters by transitioning from exact timing analysis to approximate delay modeling using lookup tables with pre-stored delay values. This parameter change allows the synthesis tool to evaluate timing constraints rapidly across multiple process corners and modes, achieving both speed improvement and maintained timing constraint compliance through statistical sampling and approximation techniques.
2Reliability
If accurate delay models are used to model actual cell delays, then timing violations can be reduced in circuit implementation, but the delay model becomes more complex and computationally intensive
Solution Approach 1:
The patent applies copying by creating simplified lookup table representations of actual cell delay characteristics measured or simulated at multiple process corners. Instead of using complex analytical delay models, the patent copies pre-computed delay data into lookup tables that can be queried efficiently during synthesis, maintaining timing accuracy while reducing model complexity and computational burden.
Solution Approach 2:
The patent uses preliminary action by pre-characterizing cells and storing their delay properties in lookup tables before synthesis. This pre-computation captures the complex timing behavior of cells across process variations, allowing the synthesis tool to use simple table lookups instead of complex real-time calculations, thus reducing model complexity while maintaining timing accuracy.
Data Source
AI summary
Systems and techniques are described for estimating optimal gate sizes in a circuit design using numerical delay models of cells and cell types in a technology library. Gate sizes are optimized in the circuit design in a reverse-levelized processing order. Gates that are at the same level in the reverse-levelized processing order, and whose inputs are electrically connected to the same driver output are optimized together. A closed-form expression is used to determine the optimized size for each gate in a set of gates that are optimized together. Some embodiments perform multiple optimization iterations, wherein in each optimization iteration all of the gates in the circuit design are processed in the reverse-levelized processing order. The iterative optimization process terminates when one or more termination conditions are met.