Gate Sizing Optimization Using Constraints Solver
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing circuit synthesis approaches for optimizing gate sizes in Electronic Design Automation (EDA) are computationally expensive and often produce poor results due to the iterative trial-and-error method, especially when dealing with modern technology libraries having many gate sizes and varying driving capabilities.
Innovation Solution
The use of a constraints solver, such as an ATPG-based word-level constraints solver, to create and solve a constraints problem based on the gate-sizing optimization problem, with upper and lower bounds adjusted iteratively to converge on optimal gate sizes, allowing for efficient optimization of circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error approaches are used to optimize gate sizes, then timing constraints can be checked and satisfied, but computational expense increases significantly and solution quality deteriorates for large circuit designs
Solution Approach 1:
The patent transforms the gate-sizing optimization problem by changing parameters from discrete gate sizes to continuous capacitance variables. This allows the use of mathematical optimization techniques instead of iterative trial-and-error, significantly improving computational efficiency while maintaining timing constraint satisfaction. The objective function and constraints are formulated in terms of capacitance values that can be directly optimized.
Solution Approach 2:
The patent replaces the mechanical iterative trial-and-error process with a mathematical constraints solver. Instead of repeatedly simulating and checking timing constraints with different gate sizes, the system formulates the problem as a set of mathematical constraints and uses automated solvers to find optimal solutions, eliminating the need for repeated computational iterations.
2Manufacturing precision
If iterative trial-and-error approaches are used to optimize gate sizes, then cell sizes can be adjusted to meet timing requirements, but the optimization process takes too long to complete
Solution Approach 1:
The patent performs preliminary formulation of the optimization problem by defining the objective function and constraints in terms of capacitance variables before solving. This preliminary mathematical modeling allows the constraints solver to directly compute optimal values without requiring iterative adjustments, significantly reducing execution time while maintaining optimization quality.
Solution Approach 2:
The patent substitutes the time-consuming iterative trial-and-error process with a mathematical constraints solver that computes optimal gate sizes directly. By formulating the problem mathematically with capacitance variables as the primary optimization target, the system eliminates repeated simulations and timing checks, reducing execution time from potentially hours to seconds or minutes.
3Adaptability or versatility
If modern technology libraries with many gate sizes are used, then design flexibility and performance options increase, but the complexity and computational cost of optimization increases
Solution Approach 1:
The patent simplifies the optimization problem by changing the parameter from discrete gate size selection to continuous capacitance variable optimization. Instead of evaluating many discrete gate sizes from the technology library, the system optimizes capacitance values mathematically and then maps the results to appropriate library cells, reducing problem complexity while maintaining design flexibility.
Solution Approach 2:
The patent introduces capacitance variables as an intermediary between the optimization process and the discrete gate size selection. The constraints solver optimizes continuous capacitance values, which then serve as guidance for selecting appropriate gate sizes from the technology library. This intermediary approach decouples the complex discrete optimization from the continuous mathematical optimization, making the problem more tractable.
Data Source
AI summary
A constraints problem can be created based on a gate-sizing optimization problem for a portion of a circuit design. The constraints problem can comprise a set of upper bound constraints that impose an upper bound on one or more variables that are used in the objective function of the gate-sizing optimization problem. The constraints problem can be repeatedly solved using a constraints solver to obtain a solution of the gate-sizing optimization problem. Specifically, prior to each invocation of the constraints solver, the upper bound can be increased or decreased based at least on a result returned by a previous invocation of the constraints solver.