Gate Sizing Optimization via Load-and-Slew-Independent Delay Models
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Solution Overview
Problem
Existing circuit synthesis approaches, such as iterative trial-and-error methods, are inefficient and produce suboptimal results for large circuit designs due to inaccurate delay modeling and assumptions about available gate sizes and path lengths, leading to many timing violations.
Innovation Solution
The use of load-and-slew-independent numerical delay models for optimizing gate sizes by selecting a driver gate and its fan-out cone, modeling the gate optimization problem with specific and generic delay models, and solving it using a numerical solver, which improves the accuracy of cell sizing and reduces timing violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If iterative trial-and-error based circuit synthesis approaches are used, then the circuit design can be optimized, but the optimization process takes too long and produces poor quality results for large circuit designs
Solution Approach 1:
The patent changes the parameter representation from discrete cell sizes to continuous sizing parameters. By formulating cell sizing as a continuous optimization problem rather than discrete trial-and-error, the method achieves both faster convergence and higher precision in meeting timing constraints.
Solution Approach 2:
The patent replaces the mechanical trial-and-error iteration process with a numerical optimization solver. Instead of physically trying different cell sizes sequentially, the system uses mathematical optimization algorithms to directly compute optimal sizing parameters, dramatically improving efficiency.
2Device complexity
If the linear delay model (d=g·h+p) is used, then the delay modeling is computationally simple, but the model is approximate and does not accurately model actual cell delays
Solution Approach 1:
The patent transforms the delay model parameters from abstract logical effort values to physically meaningful continuous parameters (output resistance R and input capacitance Ci). This parameter transformation enables accurate delay prediction while maintaining computational efficiency through the simplified linear relationship d=R·Ci+p.
3Ease of manufacture
If discrete library cells are used for optimization, then the implementation is practical, but the optimization quality is limited by the available discrete cell sizes
Solution Approach 1:
The patent performs preliminary continuous optimization to determine ideal cell sizing parameters before final discretization. By first solving the optimization problem in continuous space and then mapping results to discrete library cells, the method achieves near-optimal sizing precision while maintaining implementation practicality.
Solution Approach 2:
The patent introduces continuous sizing parameters as an intermediary between the optimization objective and discrete library cell selection. This intermediary layer allows precise optimization calculations while enabling practical implementation through rounding or selection of nearest discrete cell sizes.
Data Source
AI summary
Systems and techniques are described for optimizing a circuit design. Specifically, gate sizes in the circuit design are optimized by iteratively performing a set of operations that include, but are not limited to: selecting a portion of the circuit design (e.g., according to a reverse-levelized processing order), selecting an input-to-output arc of a driver gate in the portion of the circuit design, selecting gates in the portion of the circuit design for optimization, modeling a gate optimization problem based on the selected input-to-output arc of the driver gate and the selected gates, solving the gate optimization problem to obtain a solution using one or more solvers, and discretizing the solution. Discretizing the solution involves identifying library cells that exactly or closely match the gate sizes specified in the solution. These library cells can then be used to model other gate optimization problems in the current or subsequent iterations.