Gate Sizing Optimization Using Log-Sum-Exp Approximation
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Solution Overview
Problem
Existing circuit synthesis approaches are computationally expensive and produce poor quality results due to inaccurate delay modeling, especially when dealing with large circuit designs and multiple process corners and modes, leading to many timing violations.
Innovation Solution
The use of a numerical solver, such as a conjugate-gradient based solver, to optimize gate sizes by modeling gate optimization problems and employing the log-sum-exp function to approximate the non-differentiable 'max' function, while ensuring the parameter α does not cause overflow or underflow errors, thereby accurately minimizing the maximum delay in the circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error based circuit synthesis approaches are used to optimize gate sizes, then timing constraints can be checked across multiple process corners and modes, but the computational expense increases significantly and the process takes too long to complete
Solution Approach 1:
The patent replaces the iterative trial-and-error mechanical optimization process with a numerical solver that uses gradient-based methods. The numerical solver continuously adjusts gate sizes based on calculated gradients of the objective function, eliminating the need for repeated discrete trials and significantly reducing computational time while maintaining timing constraint satisfaction across multiple process corners.
Solution Approach 2:
The patent transforms the discrete gate sizing problem into a continuous optimization problem by changing the parameter representation. Instead of iterating through discrete gate size options, the numerical solver operates on continuous size parameters, allowing for smoother optimization convergence and reduced computational expense while achieving the same timing constraint verification.
2Reliability
If iterative trial-and-error based circuit synthesis approaches are used to optimize gate sizes, then timing constraints can be checked across multiple process corners and modes, but the quality of results becomes poor for large circuit designs
Solution Approach 1:
The patent replaces the mechanical iterative search process with a numerical optimization system that calculates gradients and adjusts gate sizes continuously. This substitution enables precise control over gate sizing parameters, achieving superior accuracy in large circuit designs by following the gradient descent path to the optimal solution rather than relying on discrete trial outcomes.
Solution Approach 2:
The numerical solver incorporates feedback mechanisms where the objective function continuously evaluates timing constraints and feeds this information back into the optimization process. The gradient calculation provides real-time feedback on how gate size changes affect timing, allowing for precise adjustments that improve manufacturing precision and achieve better timing constraint satisfaction.
3Ease of operation
If the log-sum-exp function is used to approximate the non-differentiable 'max' function, then the objective function becomes differentiable and can be solved by numerical solvers, but the parameter α may cause overflow or underflow errors
Solution Approach 1:
The patent applies parameter transformations to the log-sum-exp function by adjusting the parameter α to values that maintain numerical stability. The optimization process dynamically selects appropriate α values that balance differentiability with numerical reliability, preventing overflow and underflow errors while preserving the gradient-based optimization capability.
Solution Approach 2:
The patent introduces an intermediary scaling factor that mediates between the log-sum-exp approximation and the actual max function behavior. This intermediary parameter allows the objective function to maintain differentiability for numerical solver compatibility while the scaling factor prevents numerical instability by keeping intermediate values within safe ranges.
Data Source
AI summary
Systems and techniques are described for optimizing a circuit design by using a numerical solver. Some embodiments construct a set of lower bound expressions for a parameter that is used in an approximation of an objective function. Next, the embodiments evaluate the set of lower bound expressions to obtain a set of lower bound values. The embodiments then determine a maximum lower bound value from the set of lower bound values. Next, while solving a gate sizing problem using the numerical solver, the embodiments evaluate the approximate objective function and the partial derivatives of the approximate objective function by using the maximum lower bound value of the parameter. The maximum lower bound value of this parameter determines the accuracy of the approximation of the objective function.