Gate-to-Source/Drain Contact Structure for Integrated Circuits
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Solution Overview
Problem
In modern integrated circuits, forming a gate-to-source/drain (GSD) contact structure that effectively contacts the gate electrode and epitaxial semiconductor material in the source/drain region is challenging, often resulting in gaps that lead to device failure and reduced yields due to shrinking device dimensions.
Innovation Solution
A method involving etching processes to expose the gate electrode and source/drain regions, followed by material growth to form a conductive GSD contact structure comprising non-single crystal material on the gate electrode and single crystal material in the source/drain region, ensuring electrical coupling between the gate and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a GSD contact structure is formed with larger lateral width to ensure contact, then electrical connectivity is improved, but device packing density deteriorates
Solution Approach 1:
The patent applies local quality by forming the GSD contact structure only in specific locations where gate-to-source/drain contact is required, rather than uniformly across all devices. The contact structure is localized to areas where the gate electrode needs to contact the source or drain region, allowing other areas to maintain higher packing density without compromising necessary electrical connectivity.
2Productivity
If device dimensions are shrunk to increase packing density, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent employs preliminary action by performing etching processes to expose the gate electrode and source/drain regions before forming the GSD contact structure. This preparatory exposure ensures that subsequent material deposition and contact formation occur at precisely the right locations and times, maintaining manufacturing precision even as device dimensions shrink and packing density increases.
3Reliability
If a separate source/drain contact structure is formed for each source/drain region, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The patent merges the gate contact and source/drain contact functions into a single GSD contact structure. Instead of forming separate contact structures for the gate and for each source/drain region, the invention combines these into one integrated contact structure that simultaneously provides gate contact and source/drain contact, thereby reducing device complexity while maintaining necessary electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the likelihood of gaps between the GSD contact structure and epitaxial semiconductor material, enhancing device reliability and yield by providing a conductive path with a smaller lateral width, allowing for higher packing densities and improved electrical connectivity.
Implementation Method 1
performing at least one etching process to expose at least a portion of an upper surface of a gate electrode
Implementation Method 2
performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure
Data Source
AI summary
One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.