Gate Spacer Aspect Ratio Reduction for Dielectric Void Prevention
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Solution Overview
Problem
The formation of voids in the interlayer dielectric layer between gate structures in integrated circuits, particularly in high-aspect-ratio stacked gate architectures, poses a challenge as it hinders effective dielectric material filling and can damage underlying sensitive structures.
Innovation Solution
The method involves decreasing the aspect ratio of the gap between sidewall spacers by selective etching of the top portion of the spacers, using a mask layer to shield the base from etchants, thereby minimizing void formation in the interlayer dielectric layer without impacting the underlying structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gap spacing between gate structures is decreased to increase transistor density, then the transistor density is improved, but the aspect ratio between gate height and gap width increases making dielectric material filling difficult and causing void formation
Solution Approach 1:
The patent segments the gap filling process into two distinct phases: first filling the upper portion of the gap with dielectric material, then filling the lower portion. This segmentation allows each filling operation to be optimized independently, preventing void formation in high-aspect-ratio gaps while maintaining increased transistor density.
Solution Approach 2:
The patent applies preliminary actions by forming a mandrel structure in the gap before dielectric material deposition. This mandrel serves as a temporary support structure that prevents void formation during the first dielectric filling operation, and is subsequently removed to allow complete gap filling without defects.
2Manufacturing precision
If the aspect ratio between gate height and gap width is increased to decrease critical dimension, then the critical dimension is reduced, but void formation in the interlayer dielectric layer occurs
Solution Approach 1:
The mandrel structure is formed in advance as a preliminary action to support dielectric material deposition in high-aspect-ratio gaps. This preliminary structure prevents void formation during the filling process, ensuring the reliability of the interlayer dielectric layer is maintained even when critical dimensions are reduced.
Solution Approach 2:
The patent changes the physical parameters of the gap filling process by introducing a mandrel structure that modifies the effective aspect ratio during deposition. This parameter change allows complete filling of high-aspect-ratio gaps without void formation, maintaining dielectric layer integrity while enabling smaller critical dimensions.
3Quantity of substance
If the gap spacing between gate structures is decreased to increase transistor density, then the transistor density is improved, but the difficulty of gap fill with dielectric material increases
Solution Approach 1:
The gap fill process is segmented into multiple manageable steps: mandrel formation, first dielectric deposition, mandrel removal, and second dielectric deposition. This segmentation transforms a single difficult high-aspect-ratio filling operation into several easier steps, each with optimized parameters, thereby maintaining ease of manufacture while achieving increased transistor density.
Solution Approach 2:
The mandrel structure is formed as a preliminary action to simplify the subsequent dielectric filling process. This preliminary structure provides a template that guides dielectric material deposition, making the gap fill process easier to control and execute, especially in high-aspect-ratio geometries required for increased transistor density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces void formation in the interlayer dielectric layer while maintaining the aspect ratio at the base of the sidewall spacers, ensuring effective dielectric filling and protecting sensitive structures.
Implementation Method 1
The top portion of the sidewall spacers is etched with an etchant that is selective to the sidewall spacers as compared to the mask layer
Implementation Method 2
A mask layer is formed in the gap between the sidewall spacers... a bottom portion of the sidewall spacers is covered by the mask layer after forming the mask layer
Data Source
AI summary
Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.