Gate Spacer Reinforcement for Source/Drain Contact Isolation
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Solution Overview
Problem
The existing semiconductor fabrication process results in spacers with thinner upper portions, leading to potential shorting of the gate to the source or drain regions, degrading device performance.
Innovation Solution
A method is introduced to form second spacers on the thinner upper portions of first spacers, thickening these areas to prevent shorting, involving partial removal of the first interlayer dielectric layer and application of a second spacer material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the spacer material layer is etched away from the top of the gate structure and source or drain regions, then the spacers are formed on the sidewalls of the gate structure, but the upper portions of the spacers become thinner, leading to potential gate shorting
Solution Approach 1:
The spacer formation process is divided into two separate etching steps: a first etching step that forms initial spacers with sufficient thickness, and a second etching step that refines the spacer shape. This segmentation allows the upper portion thickness to be independently controlled, ensuring both adequate thickness for isolation and proper geometric profile for device performance.
Solution Approach 2:
The first etching step performs a preliminary spacer formation with controlled thickness before the final shaping step. By establishing the baseline spacer thickness early in the process, the method ensures that sufficient material remains to prevent gate shorting, while subsequent steps refine the geometry without compromising the critical thickness parameter.
2Ease of manufacture
If the spacer material layer is completely removed from the top surfaces, then clean sidewall spacers are formed, but the gate may short to source or drain regions at locations where spacers are thinner
Solution Approach 1:
The first etching step is designed to remove excess spacer material from top surfaces in advance, preventing potential shorting paths before they can form. By proactively eliminating material from regions where shorting could occur, the process counteracts the harmful effect before it manifests in the final device structure.
Solution Approach 2:
The etching process is optimized to differentially remove material from different locations: aggressive removal from top surfaces where shorting risk exists, while preserving sufficient thickness on sidewalls where the spacer provides essential isolation. This localized control of material removal addresses the specific geometric requirements of different regions.
Data Source
AI summary
A semiconductor device and a method for fabricating it are disclosed. The method includes: providing a substrate, on which a gate structure, first spacers on opposite sidewalls of the gate structure, source/drain regions in the substrate on opposite sides of the first spacers and a first interlayer dielectric layer are formed, wherein upper portions of the first spacers proximal to their tops are thinner than the remaining portions of the first spacers; removing a portion of the first interlayer dielectric layer, exposing at least a part of the upper portions of the first spacers; forming second spacers on exposed upper portions of the first spacers; forming a second interlayer dielectric layer, which covers the first interlayer dielectric layer and the gate structure; and forming contact plugs in the second interlayer dielectric layer and the first interlayer dielectric layer, which contact the source/drain regions.