Gate Spacer and Dam Structure for Controlled Source/Drain Growth
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved reliability and integration density.
Innovation Solution
A semiconductor device design featuring a substrate with active patterns defined by trenches, device isolation layers, source/drain patterns, partition walls, dam structures, and gate cutting patterns, along with a gate spacer with varying thicknesses, and a method involving selective epitaxial growth and sacrificial layer processing to inhibit horizontal growth of source/drain patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS-FETs are scaled down to increase integration density, then integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel structures. Multiple channel patterns are stacked vertically to increase the effective channel area without increasing the lateral footprint, thereby improving integration density while maintaining operational performance through enhanced channel control
Solution Approach 2:
The active region is divided into multiple discrete channel patterns stacked vertically, with each channel pattern separated by partition walls. This segmentation allows independent formation and control of each channel, enabling higher integration density while maintaining reliable electrical characteristics for each individual channel
2Ease of manufacture
If source/drain patterns are allowed to grow horizontally, then manufacturing simplicity is improved, but device reliability deteriorates due to unintended expansion
Solution Approach 1:
Dam structures are introduced as intermediary elements positioned between adjacent active patterns. These dam structures act as physical barriers that prevent horizontal expansion of source/drain patterns during epitaxial growth, ensuring precise pattern definition while allowing straightforward manufacturing processes
Solution Approach 2:
The dam structures are formed in advance before source/drain pattern growth to preemptively block horizontal expansion. This preliminary anti-action prevents unintended pattern expansion before it can occur during the epitaxial growth process, maintaining pattern precision without complex process control
3Quantity of substance
If cell height is reduced to increase integration density, then integration density is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent utilizes vertical stacking to increase the effective device area without increasing cell footprint. By arranging multiple channel patterns in the vertical dimension, integration density is improved while maintaining sufficient lateral dimensions for precise pattern formation and manufacturing control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability and integration density of semiconductor devices by preventing horizontal expansion of source/drain patterns, reducing cell height, and increasing integration density while maintaining operational efficiency.
Implementation Method 1
forming a source/drain pattern in the recess. The forming of the source/drain pattern may include a selective epitaxial growth process
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern that is defined by a trench, a device isolation layer in the trench, a first source/drain pattern and a second source/drain pattern on the active pattern, a partition wall between the first and second source/drain patterns, a dam structure and a gate cutting pattern on the device isolation layer, and a gate spacer on a side surface of the gate cutting pattern. The first source/drain pattern is in a recess between the partition wall and the dam structure, and a lower portion of the gate spacer is interposed between the dam structure and the gate cutting pattern. A first thickness of the lower portion of the gate spacer is different from a second thickness of an upper portion of the gate spacer.