Gate Spacer Doping Gradient for Lower Dielectric Constant
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Solution Overview
Problem
The increasing complexity and scaling down of integrated circuits (ICs) lead to challenges in reducing the dielectric constant of gate spacers, which affects device performance and efficiency.
Innovation Solution
A method involving the use of dopants such as fluorine, nitrogen, hydrogen, or carbon to diffuse into gate spacers, reducing their dielectric constants through annealing processes, thereby improving carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate spacer dimensions are reduced to enable IC scaling, then device density increases, but dielectric constant reduction becomes more difficult and device performance deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the dielectric constant of gate spacers through dopant incorporation. Specifically, fluorine, nitrogen, hydrogen, or carbon dopants are introduced to reduce the dielectric constant from typical values (e.g., Si3N4 with k≈7.5) to lower values, thereby reducing parasitic capacitance and improving RC delay in scaled devices while maintaining the physical dimensions needed for high density
Solution Approach 2:
The patent applies local quality by selectively doping only the gate spacer regions adjacent to the channel, rather than uniformly modifying the entire structure. The dopant concentration is highest near the channel interface where it most effectively reduces parasitic capacitance, while maintaining appropriate dielectric properties in other regions
2Ease of manufacture
If conventional dielectric materials are used in gate spacers, then manufacturing is simpler, but parasitic capacitance increases and RC delay worsens
Solution Approach 1:
The patent applies preliminary action by incorporating dopants into the gate spacer material during the spacer formation process itself, rather than requiring separate post-processing steps. The dopant source layer is formed conformally over the gate structure, and a single annealing step simultaneously activates the dopants and reduces the dielectric constant, streamlining the manufacturing process
Solution Approach 2:
The patent changes the physical and chemical parameters of the dielectric material by incorporating dopants that reduce the dielectric constant. This allows the use of conventional spacer materials (such as silicon nitride or silicon oxide) with modified electrical properties, achieving lower parasitic capacitance without fundamentally changing the manufacturing process flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric constants of gate spacers are reduced, enhancing carrier mobility and overall device performance by up to 25%, thus addressing the challenges of scaling down in ICs.
Implementation Method 1
diffuse k-value reduction impurities from the dopant source layer into the gate spacers
Implementation Method 2
annealing the dopant source layer to diffuse k-value reduction impurities
Data Source
AI summary
A semiconductor device includes a substrate, a gate stack over the substrate and a gate spacer on a sidewall of the gate stack. The gate spacer includes an outer spacer and an inner spacer between the gate stack and the outer spacer. The outer spacer and the inner spacer have same k-value reduction impurities, and a concentration of the k-value reduction impurities in the inner spacer is greater than a concentration of the k-value reduction impurities in the outer spacer.