Gate Spacer Ion Implantation to Reduce ILD Etch Loss
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the inadvertent damage to gate spacers during the etching of interlayer dielectric layers in FET fabrication, leading to potential shorting issues between gate structures and conductive components due to the close proximity and reduced feature sizes in IC devices.
Innovation Solution
A method involving a two-step implantation process for the gate spacer material, where silicon atoms are first implanted to create a silicon-rich layer, followed by carbon implantation to form a SiC-rich layer, which increases the etching selectivity and resistance of the gate spacer relative to the interlayer dielectric layer, thereby minimizing loss during subsequent processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the interlayer dielectric layer is etched to accommodate subsequent processing, then the processing can proceed as planned, but the gate spacer is inadvertently damaged due to close proximity and reduced feature sizes
Solution Approach 1:
The gate spacer is modified with a silicon-rich layer formed by ion implantation in a specific region (the upper portion exposed during etching). This creates a localized property change where only the critical area adjacent to the ILD layer has enhanced etching resistance, while the rest of the gate spacer maintains its original properties. This resolves the contradiction by providing targeted protection exactly where the etching harm occurs.
Solution Approach 2:
The silicon ion implantation is performed before the ILD layer etching process. This preliminary modification of the gate spacer creates a protective silicon-rich layer that will be present when the etching occurs, preventing the inadvertent damage that would otherwise happen during the subsequent etching step. The protective action is taken in advance, before the harmful etching process begins.
2Productivity
If feature sizes are reduced to increase functional density, then production efficiency increases and costs decrease, but the gate spacer becomes more susceptible to damage during ILD etching
Solution Approach 1:
The physical-chemical parameters of the gate spacer are changed by introducing a silicon-rich layer through ion implantation. This alters the composition and etching characteristics of the gate spacer material in the critical region, making it more resistant to the etching process. The parameter change (increased silicon concentration) directly addresses the vulnerability caused by reduced feature sizes while maintaining the benefits of scaling.
3Ease of manufacture
If conventional etching processes are used on the interlayer dielectric layer, then the etching can be completed, but loss of gate spacer material occurs leading to potential shorting issues
Solution Approach 1:
The silicon ion implantation process, which modifies the gate spacer composition, converts the potential harm of etching damage into a benefit of enhanced etching resistance. The same etching process that would normally remove gate spacer material is transformed into a process that selectively removes only the ILD layer while leaving the silicon-enriched gate spacer region intact. The harmful etching action is thus converted into a beneficial selective removal process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces gate spacer loss and enhances etching selectivity, ensuring the integrity of the gate spacer during interlayer dielectric etching and subsequent processing, thereby preventing shorting issues and improving the overall reliability of the semiconductor device.
Implementation Method 1
performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms
Implementation Method 2
performing a second implantation process to the upper portion of the gate spacer, wherein the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms
Data Source
AI summary
A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.